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regarding the change of names mentioned in the document, such as mitsubishi electric and mitsubishi xx, to renesas technology corp. the semiconductor operations of hitachi and mitsubishi electric were transferred to renesas technology corporation on april 1st 2003. these operations include microcomputer, logic, analog and discrete devices, and memory chips other than drams (flash memory, srams etc.) accordingly, although mitsubishi electric, mitsubishi electric corporation, mitsubishi semiconductors, and other mitsubishi brand names are mentioned in the document, these names have in fact all been changed to renesas technology corp. thank you for your understanding. except for our corporate trademark, logo and corporate statement, no changes whatsoever have been made to the contents of the document, and these changes do not constitute any alteration to the contents of the document itself. note : mitsubishi electric will continue the business operations of high frequency & optical devices and power devices. renesas technology corp. customer support dept. april 1, 2003 to all our customers
mitsubishi 16-bit single-chip microcomputer 7700 family / 7751 series 7751 group users manual
this manual describes the hardware of the mitsubishi cmos 16-bit microcomputers 7751 group. after reading this manual, the users will be able to understand the functions, so that they can utilize their capabilities fully. for details concerning the software, refer to the 7751 series software manual. for details concerning the development support tools (assembler, emulation pods), refer to the respective users manuals. preface
table of contents i 7751 group users manual table of contents chapter 1. description 1.1 performance overview .......................................................................................................... 1-3 1.2 pin configuration ................................................................................................................... 1-4 1.3 pin description ...................................................................................................................... 1-5 1.4 block diagram ........................................................................................................................ 1-8 chapter 2. central processing unit (cpu) 2.1 central processing unit ....................................................................................................... 2-2 2.1.1 accumulator (acc) ......................................................................................................... 2-3 2.1.2 index register x (x) ....................................................................................................... 2-3 2.1.3 index register y (y) ....................................................................................................... 2-3 2.1.4 stack pointer (s) ............................................................................................................ 2-4 2.1.5 program counter (pc) ................................................................................................... 2-5 2.1.6 program bank register (pg) ......................................................................................... 2-5 2.1.7 data bank register (dt) ................................................................................................ 2-6 2.1.8 direct page register (dpr) ........................................................................................... 2-6 2.1.9 processor status register (ps) ..................................................................................... 2-8 2.2 bus interface unit ............................................................................................................... 2-10 2.2.1 overview ....................................................................................................................... 2-10 2.2.2 functions of bus interface unit (biu) ........................................................................ 2-12 2.2.3 operation of bus interface unit (biu) ........................................................................ 2-15 2.3 access space ....................................................................................................................... 2-17 2.3.1 banks ............................................................................................................................ 2-18 2.3.2 direct page ................................................................................................................... 2-18 2.4 memory assignment ........................................................................................................... 2-19 2.4.1 memory assignment in internal area ......................................................................... 2-19 2.5 processor modes ................................................................................................................ 2-22 2.5.1 single-chip mode ......................................................................................................... 2-23 2.5.2 memory expansion and microprocessor modes ....................................................... 2-23 2.5.3 setting processor modes ............................................................................................ 2-26 [precautions when operating in single-chip mode] ............................................................ 2-28 chapter 3. input/output pins 3.1 programmable i/o ports ...................................................................................................... 3-2 3.1.1 direction register ............................................................................................................ 3-3 3.1.2 port register .................................................................................................................... 3-4 3.2 i/o pins of internal peripheral devices ............................................................................ 3-8
table of contents ii 7751 group users manual chapter 4. interrupts 4.1 overview ..................................................................................................................................4-2 4.2 interrupt sources ................................................................................................................... 4-4 4.3 interrupt control .................................................................................................................... 4-6 4.3.1 interrupt disable flag (i) ................................................................................................ 4-8 4.3.2 interrupt request bit ....................................................................................................... 4-8 4.3.3 interrupt priority level select bits and processor interrupt priority level (ipl) ....... 4-8 4.4 interrupt priority level ........................................................................................................ 4-10 4.5 interrupt priority level detection circuit ........................................................................ 4-11 4.6 interrupt priority level detection time ............................................................................ 4-13 4.7 sequence from acceptance of interrupt request to execution of interrupt routine ........................... 4-14 4.7.1 change in ipl at acceptance of interrupt request .................................................. 4-16 4.7.2 storing registers ........................................................................................................... 4-17 4.8 return from interrupt routine ........................................................................................... 4-18 4.9 multiple interrupts ............................................................................................................... 4-18 ___ 4.10 external interrupts (int i interrupt) ................................................................................ 4-20 ___ 4.10.1 function of int i interrupt request bit ...................................................................... 4-23 ___ 4.10.2 switch of occurrence factor of int i interrupt request ........................................... 4-25 chapter 5. timer a 5.1 overview ..................................................................................................................................5-2 5.2 block description .................................................................................................................. 5-3 5.2.1 counter and reload register (timer ai register) ......................................................... 5-4 5.2.2 count start register ........................................................................................................ 5-5 5.2.3 timer ai mode register ................................................................................................. 5-6 5.2.4 timer ai interrupt control register ............................................................................... 5-7 5.2.5 port p5 and port p6 direction registers ..................................................................... 5-8 5.3 timer mode ............................................................................................................................ 5-9 5.3.1 setting for timer mode ................................................................................................ 5-11 5.3.2 count source ................................................................................................................ 5-13 5.3.3 operation in timer mode ............................................................................................. 5-14 5.3.4 select function ............................................................................................................. 5-15 5.4 event counter mode ........................................................................................................... 5-19 5.4.1 setting for event counter mode ................................................................................. 5-22 5.4.2 operation in event counter mode .............................................................................. 5-24 5.4.3 select functions ............................................................................................................ 5-26 5.5 one-shot pulse mode ......................................................................................................... 5-30 5.5.1 setting for one-shot pulse mode ............................................................................... 5-32 5.5.2 count source ................................................................................................................ 5-34 5.5.3 trigger ........................................................................................................................... 5-35 5.5.4 operation in one-shot pulse mode ............................................................................ 5-36 5.6 pulse width modulation (pwm) mode ............................................................................ 5-39 5.6.1 setting for pwm mode ............................................................................................... 5-41 5.6.2 count source ................................................................................................................ 5-43 5.6.3 trigger ........................................................................................................................... 5-43 5.6.4 operation in pwm mode ............................................................................................ 5-44
table of contents iii 7751 group users manual chapter 6. timer b 6.1 overview ..................................................................................................................................6-2 6.2 block description .................................................................................................................. 6-2 6.2.1 counter and reload register (timer bi register) ......................................................... 6-3 6.2.2 count start register ........................................................................................................ 6-4 6.2.3 timer bi mode register ................................................................................................. 6-5 6.2.4 timer bi interrupt control register ............................................................................... 6-6 6.2.5 port p6 direction register ............................................................................................. 6-7 6.3 timer mode ............................................................................................................................ 6-8 6.3.1 setting for timer mode ................................................................................................ 6-10 6.3.2 count source ................................................................................................................ 6-11 6.3.3 operation in timer mode ............................................................................................. 6-12 6.4 event counter mode ........................................................................................................... 6-14 6.4.1 setting for event counter mode ................................................................................. 6-16 6.4.2 operation in event counter mode .............................................................................. 6-17 6.5 pulse period/pulse width measurement mode ............................................................. 6-19 6.5.1 setting for pulse period/pulse width measurement mode ...................................... 6-21 6.5.2 count source ................................................................................................................ 6-23 6.5.3 operation in pulse period/pulse width measurement mode ................................... 6-24 chapter 7. serial i/o 7.1 overview ..................................................................................................................................7-2 7.2 block description .................................................................................................................. 7-3 7.2.1 uarti transmit/receive mode register ........................................................................ 7-4 7.2.2 uarti transmit/receive control register 0 .................................................................. 7-6 7.2.3 uarti transmit/receive control register 1 .................................................................. 7-7 7.2.4 uarti transmit register and uarti transmit buffer register ................................... 7-9 7.2.5 uarti receive register and uarti receive buffer register .................................... 7-11 7.2.6 uarti baud rate register (brgi) .............................................................................. 7-13 7.2.7 uarti transmit interrupt control and uarti receive interrupt control registers 7-14 7.2.8 port p8 direction register ........................................................................................... 7-16 7.3 clock synchronous serial i/o mode ............................................................................... 7-17 7.3.1 transfer clock (synchronizing clock) ......................................................................... 7-18 7.3.2 transfer data format .................................................................................................... 7-19 7.3.3 method of transmission ............................................................................................... 7-20 7.3.4 transmit operation ....................................................................................................... 7-24 7.3.5 method of reception .................................................................................................... 7-26 7.3.6 receive operation ........................................................................................................ 7-30 7.3.7 process on detecting overrun error ........................................................................... 7-33 7.4 clock asynchronous serial i/o (uart) mode ............................................................... 7-35 7.4.1 transfer rate (frequency of transfer clock) .............................................................. 7-36 7.4.2 transfer data format .................................................................................................... 7-38 7.4.3 method of transmission ............................................................................................... 7-40 7.4.4 transmit operation ....................................................................................................... 7-44 7.4.5 method of reception .................................................................................................... 7-46 7.4.6 receive operation ........................................................................................................ 7-49 7.4.7 process on detecting error ......................................................................................... 7-51 7.4.8 sleep mode .................................................................................................................. 7-52
table of contents iv 7751 group users manual chapter 8. a-d converter 8.1 overview ..................................................................................................................................8-2 8.2 block description .................................................................................................................. 8-3 8.2.1 a-d control register 0 ................................................................................................... 8-4 8.2.2 a-d control register 1 ................................................................................................... 8-6 8.2.3 a-d register i (i = 0 to 7) ............................................................................................. 8-7 8.2.4 a-d conversion interrupt control register .................................................................... 8-8 8.2.5 port p7 direction register ............................................................................................. 8-9 8.3 a-d conversion method (successive approximation conversion method) ............ 8-10 8.4 absolute accuracy and differential non-linearity error .............................................. 8-13 8.4.1 absolute accuracy ....................................................................................................... 8-13 8.4.2 differential non-linearity error ..................................................................................... 8-14 8.5 comparison voltage in 8-bit mode ................................................................................. 8-15 8.6 one-shot mode .................................................................................................................... 8-16 8.6.1 settings for one-shot mode ........................................................................................ 8-16 8.6.2 one-shot mode operation description ....................................................................... 8-18 8.7 repeat mode ........................................................................................................................ 8-20 8.7.1 settings for repeat mode ............................................................................................ 8-20 8.7.2 repeat mode operation description .......................................................................... 8-22 8.8 single sweep mode ............................................................................................................ 8-23 8.8.1 settings for single sweep mode ................................................................................ 8-23 8.8.2 single sweep mode operation description ................................................................ 8-25 8.9 repeat sweep mode 0 ....................................................................................................... 8-27 8.9.1 settings for repeat sweep mode 0 ............................................................................ 8-27 8.9.2 repeat sweep mode 0 operation description .......................................................... 8-29 8.10 repeat sweep mode 1 ..................................................................................................... 8-31 8.10.1 settings for repeat sweep mode 1 .......................................................................... 8-31 8.10.2 repeat sweep mode 1 operation description ........................................................ 8-34 chapter 9. watchdog timer 9.1 block description .................................................................................................................. 9-2 9.1.1 watchdog timer .............................................................................................................. 9-3 9.1.2 watchdog timer frequency select register .................................................................. 9-4 9.2 operation description .......................................................................................................... 9-5 9.2.1 basic operation .............................................................................................................. 9-5 9.2.2 operation in stop mode ............................................................................................... 9-7 9.2.3 operation in hold state ................................................................................................. 9-7 9.3 precautions when using watchdog timer ........................................................................ 9-8 chapter 10. stop mode 10.1 clock generating circuit .................................................................................................. 10-2 10.2 operation description ...................................................................................................... 10-3 10.2.1 termination by interrupt request occurrence ......................................................... 10-4 10.2.2 termination by hardware reset ................................................................................ 10-5 10.3 precautions for stop mode ............................................................................................ 10-6
table of contents v 7751 group users manual chapter 11. wait mode 11.1 clock generating circuit .................................................................................................. 11-2 11.2 operation description ...................................................................................................... 11-3 11.2.1 termination by interrupt request occurrence ......................................................... 11-4 11.2.2 termination by hardware reset ................................................................................ 11-4 11.3 precautions for wait mode ............................................................................................. 11-5 chapter 12. connection with external devices 12.1 signals required for accessing external devices ...................................................... 12-2 12.1.1 descriptions of signals .............................................................................................. 12-2 12.1.2 operation of bus interface unit (biu) ..................................................................... 12-8 12.2 bus cycle .......................................................................................................................... 12-11 12.3 ready function ................................................................................................................ 12-14 12.3.1 operation description .............................................................................................. 12-15 12.4 hold function ................................................................................................................... 12-18 12.4.1 operation description .............................................................................................. 12-19 chapter 13. reset 13.1 hardware reset .................................................................................................................. 13-2 13.1.1 pin state ..................................................................................................................... 13-3 13.1.2 state of cpu, sfr area, and internal ram area ................................................. 13-4 13.1.3 internal processing sequence after reset ............................................................... 13-9 ______ 13.1.4 time supplying l level to reset pin ................................................................ 13-10 13.2 software reset .................................................................................................................. 13-12 chapter 14. clock generating circuit 14.1 oscillation circuit example ............................................................................................. 14-2 14.1.1 connection example using resonator/oscillator ...................................................... 14-2 14.1.2 input example of externally generated clock ......................................................... 14-2 14.2 clock .................................................................................................................................... 14-3 14.2.1 clock generated in clock generating circuit ........................................................... 14-4 14.2.2 operation clock for internal peripheral devices ..................................................... 14-5
table of contents vi 7751 group users manual chapter 15. electrical characteristics 15.1 absolute maximum ratings ............................................................................................. 15-2 15.2 recommended operating conditions ............................................................................ 15-3 15.3 electrical characteristics ................................................................................................. 15-4 15.4 a-d converter characteristics ........................................................................................ 15-5 15.5 internal peripheral devices ............................................................................................. 15-6 15.6 ready and hold ............................................................................................................... 15-13 15.7 single-chip mode ............................................................................................................ 15-16 15.8 memory expansion mode and microprocessor mode : when 2- f access in low-speed running ......................................................................................................... 15-18 15.9 memory expansion mode and microprocessor mode : when 3- f access in low-speed running ......................................................................................................... 15-23 15.10 memory expansion mode and microprocessor mode : when 4- f access in low-speed running ....................................................................................................... 15-28 15.11 memory expansion mode and microprocessor mode : when 3- f access in high-speed running ...................................................................................................... 15-33 15.12 memory expansion mode and microprocessor mode : when 4- f access in high-speed running ...................................................................................................... 15-38 15.13 memory expansion mode and microprocessor mode : when 5- f access in high-speed running ...................................................................................................... 15-43 15.14 memory expansion mode and microprocessor mode : when 2- f access in high-speed running (internal ram access) ............................................................ 15-48 _ 15.15 testing circuit for ports p0 to p8, f 1 , and e ......................................................... 15-51 chapter 16. standard characteristics 16.1 standard characteristics ................................................................................................. 16-2 16.1.1 programmable i/o port (cmos output) standard characteristics ........................ 16-2 16.1.2 iccCf(x in ) standard characteristics .......................................................................... 16-3 16.1.3 a-d converter standard characteristics ................................................................... 16-4 chapter 17. applications 17.1 memory expansion ............................................................................................................ 17-2 17.1.1 memory expansion model ......................................................................................... 17-2 17.1.2 how to calculate timing ............................................................................................ 17-4 17.1.3 points in memory expansion .................................................................................... 17-8 17.1.4 example of memory expansion .............................................................................. 17-26 17.1.5 example of i/o expansion ...................................................................................... 17-37
table of contents vii 7751 group users manual chapter 18. prom version 18.1 eprom mode ..................................................................................................................... 18-3 18.1.1 pin description ........................................................................................................... 18-3 18.1.2 programming/reading to/from built-in prom .......................................................... 18-4 18.1.3 programming algorithm of built-in prom ............................................................... 18-7 18.1.4 electrical characteristics of programming algorithm .............................................. 18-9 18.2 usage precaution ............................................................................................................ 18-10 18.2.1 precautions on all prom versions ....................................................................... 18-10 18.2.2 precautions on one time prom version .............................................................. 18-11 18.2.3 precautions on eprom version ............................................................................ 18-11 chapter 19. flash memory version 19.1 parallel input/output mode ............................................................................................. 19-3 19.1.1 pin description ........................................................................................................... 19-4 19.1.2 access to builtCin flash memory ............................................................................. 19-5 19.1.3 readConly mode ........................................................................................................ 19-7 19.1.4 read/write (software command control) mode ...................................................... 19-9 19.1.5 electrical characteristics ......................................................................................... 19-18 19.1.6 program/erase algorithm flow chart ...................................................................... 19-20 19.2 serial input/output mode ............................................................................................... 19-21 19.2.1 pin description ......................................................................................................... 19-21 19.2.2 access to builtCin flash memory ........................................................................... 19-23 19.2.3 electrical characteristics ......................................................................................... 19-31 19.2.4 program algorithm flow chart ................................................................................. 19-33 appendix appendix 1. memory assignment ........................................................................................... 20-2 appendix 2. memory assignment in sfr area ................................................................... 20-5 appendix 3. control registers ................................................................................................. 20-9 appendix 4. package outlines .............................................................................................. 20-32 appendix 5. example for processing unused pins .......................................................... 20-34 appendix 6. hexadecimal instruction code table ............................................................. 20-37 appendix 7. machine instructions ....................................................................................... 20-40 appendix 8. examples of noise immunity improvement ................................................ 20-61 appendix 9. q & a .................................................................................................................. 20-71
table of contents viii 7751 group users manual memorandum
chapter 1 description 1.1 performance overview 1.2 pin configuration 1.3 pin description 1.4 block diagram
description 7751 group users manual 1C2 the 16-bit single-chip microcomputers 7751 group is suitable for office, business, and industrial equipment controllers that require high-speed processing of large amounts of data. these microcomputers develop with the m37751m6c-xxxfp as the base chip. this manual describes the functions about the m37751m6c-xxxfp unless there is a specific difference and refers to the m37751m6c-xxxfp as m37751. notes 1: about details concerning each microcomputers development status of the 7751 group, inquire of contact addresses for further information described last. 2: how the 7751 groups type name see is described below. m 3 77 51 m 6 cCxxx fp mitsubishi integrated prefix represent an original single-chip microcomputer series designation using 2 digits circuit function identification code using 2 digits memory identification code using a digit m: mask rom e: eprom f: flash memory s: external rom memory size identification code using a digit difference of electrical characteristics identification code using a digit mask rom number package style fp: plastic molded qfp fs: ceramic qfn
description 7751 group users manual 1C3 1.1 performance overview 1.1 performance overview table 1.1.1 shows the performance overview of the m37751. table 1.1.1 m37751 performance overview parameters number of basic instructions instruction execution time operating clock frequency f(x in ) memory size programmable input/output ports multifunction timers serial i/o a-d converter watchdog timer interrupts clock generating circuit supply voltage power dissipation port input/output characteristics memory expansion operating temperature range device structure package rom ram p0Cp2, p4Cp8 p3 ta0Cta4 tb0Ctb2 uart0, uart1 functions 109 100 ns (the minimum instruction at f(x in ) = 40 mhz) 40 mhz (maximum at high-speed running) 49152 bytes 2048 bytes 8 bits 5 8 4 bits 5 1 16 bits 5 5 16 bits 5 3 (uart or clock synchronous serial i/o) 5 2 10-bit successive approximation method 5 1 (8 channels) 12 bits 5 1 3 external, 16 internal (priority levels 0 to 7 can be set for each interrupt with software) built-in (externally connected to a ceramic resonator or a quartz-crystal oscillator) 5 v 10 % 125 mw (at f(x in ) = 40 mhz frequency, typ.) 5 v 5 ma maximum 16 mbytes C20c to 85c cmos high-performance silicon gate process 80-pin plastic molded qfp input/output withstand voltage output current note: all of the 7751 group microcomputers are the same except for the package type, memory type, memory size, and electric characteristics.
description 7751 group users manual 1C4 1.2 pin configuration figure 1.2.1 shows the m37751 pin configuration. 1.2 pin configuration 25 27 26 28 34 29 30 31 32 33 35 36 37 38 39 40 p7 0 /an 0 p6 7 /tb2 in p6 6 /tb1 in p6 5 /tb0 in p6 4 /int 2 p6 3 /int 1 p6 2 /int 0 p6 1 /ta4 in p6 0 /ta4 out p5 7 /ta3 in p5 6 /ta3 out p5 5 /ta2 in p5 4 /ta2 out p5 3 /ta1 in p5 2 /ta1 out p5 1 /ta0 in p5 0 /ta0 out 1 4 3 2 5 p4 0 /hold byte cnv ss reset x in x out e v ss p3 3 /hlda p3 2 /ale p3 1 /bhe p3 0 /r/w p2 7 /a 23 /d 7 p2 6 /a 22 /d 6 p2 5 /a 21 /d 5 p2 4 /a 20 /d 4 p7 4 /an 4 p7 5 /an 5 p7 6 /an 6 p7 7 /an 7 /ad trg v ss av ss v ref av cc v cc p8 0 /cts 0 /rts 0 p8 1 /clk 0 p8 2 /r x d 0 p8 3 /t x d 0 p8 4 /cts 1 /rts 1 p8 5 /clk 1 p8 6 /r x d 1 p8 7 /t x d 1 p0 0 /a 0 p0 1 /a 1 p0 2 /a 2 p0 3 /a 3 p0 4 /a 4 p0 5 /a 5 p0 6 /a 6 p0 7 /a 7 p1 0 /a 8 /d 8 p1 1 /a 9 /d 9 p1 2 /a 10 /d 10 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 80 79 78 77 76 75 74 73 72 71 69 68 67 66 65 70 outline : 80p6n-a p1 3 /a 11 /d 11 p1 4 /a 12 /d 12 p1 5 /a 13 /d 13 p1 6 /a 14 /d 14 p1 7 /a 15 /d 15 p2 0 /a 16 /d 0 p2 1 /a 17 /d 1 p2 2 /a 18 /d 2 p2 3 /a 19 /d 3 43 42 41 m37751m6c-xxxfp 22 23 24 p4 1 /rdy p4 7 p4 6 p4 5 p4 4 p4 3 p4 2 / f 1 p7 1 /an 1 p7 2 /an 2 p7 3 /an 3 fig. 1.2.1 m37751 pin configuration (top view)
description 7751 group users manual 1C5 1.3 pin description tables 1.3.1 to 1.3.3 list the pin description. table 1.3.1 pin description (1) 1.3 pin description functions supply 5 v 10 % to vcc pin and 0 v to vss pin. this pin controls the processor mode. [single-chip mode] [memory expansion mode] connect to vss pin. [microprocessor mode] connect to vcc pin. the microcomputer is reset when supplying l level to this pin. these are i/o pins of the internal clock generating circuit. connect a ceramic resonator or quartz-crystal oscillator between x in and x out pins. when using an external clock, the clock source should be input to x in pin and x out pin should be left open. _ this pin outputs e signal. data/instruction code read or data write is performed when output from this pin is l level. [memory expansion mode] [microprocessor mode] input level to this pin determines whether the external data bus has a 16-bit width or 8-bit width. the width is 16 bits when the level is l, and 8 bits when the level is h. the power supply pin for the a-d converter. externally connect avcc to vcc pin. the power supply pin for the a-d converter. externally connect avss to vss pin. this is a reference voltage input pin for the a-d converter. input/output input input input output output input input name power supply cnvss reset input clock input clock output enable output external data bus width selection input analog supply input reference voltage input pin vcc, vss cnvss ______ reset x in x out _ e byte avcc avss v ref
description 7751 group users manual 1C6 table 1.3.2 pin description (2) 1.3 pin description functions [single-chip mode] port p0 is an 8-bit cmos i/o port. this port has an i/o direction register and each pin can be programmed for input or output. [memory expansion mode] [microprocessor mode] low-order 8 bits (a 0 Ca 7 ) of the address are output. [single-chip mode] port p1 is an 8-bit i/o port with the same function as p0. [memory expansion mode] [microprocessor mode] l external bus width = 8 bits (when the byte pin is h level) middle-order 8 bits (a 8 Ca 15 ) of the address are output. l external bus width = 16 bits (when the byte pin is l level) data (d 8 to d 15 ) input/output and output of the middle- order 8 bits (a 8 Ca 15 ) of the address are performed with the time sharing system. [single-chip mode] port p2 is an 8-bit i/o port with the same function as p0. [memory expansion mode] [microprocessor mode] data (d 0 to d 7 ) input/output and output of the high- order 8 bits (a 16 Ca 23 ) of the address are performed with the time sharing system. [single-chip mode] port p3 is a 4-bit i/o port with the same function as p0. [memory expansion mode] [microprocessor mode] __ ____ _____ p3 0 Cp3 3 respectively output r/w, bhe, ale, and hlda signals. __ l r/w the read/write signal indicates the data bus state. the state is read while this signal is h level, and write while this is l level. ____ l bhe l level is output when an odd-numbered address is accessed. l ale this is used to obtain only the address from address and data multiplex signals. _____ l hlda this is the signal to externally indicate the state when the microcomputer is in hold state. l level is output during hold state. input/output i/o output i/o i/o i/o output pin p0 0 Cp0 7 a 0 Ca 7 p1 0 Cp1 7 a 8 /d 8 C a 15 /d 15 p2 0 Cp2 7 a 16 /d 0 C a 23 /d 7 p3 0 Cp3 3 __ r/w, ____ bhe, ale, _____ hlda name i/o port p0 i/o port p1 i/o port p2 i/o port p3
description 7751 group users manual 1C7 1.3 pin description table 1.3.3 pin description (3) pin p4 0 Cp4 7 _____ hold, ____ rdy, p4 2 Cp4 7 _____ hold, ____ rdy, f 1 , p4 3 Cp4 7 p5 0 Cp5 7 p6 0 Cp6 7 p7 0 Cp7 7 p8 0 Cp8 7 functions [single-chip mode] port p4 is an 8-bit i/o port with the same function as p0. p4 2 can be programmed as the clock f 1 output pin. [memory expansion mode] _____ ____ p4 0 functions as the hold input pin, p4 1 as the rdy input pin. the microcomputer is in hold state while l _____ level is input to the hold pin. the microcomputer is in ready state while l level is ____ input to the rdy pin. p4 2 Cp4 7 function as i/o ports with the same functions as p0. p4 2 can be programmed for the clock f 1 output pin. [microprocessor mode] _____ ____ p4 0 functions as the hold input pin, p4 1 as the rdy input pin. p4 2 always functions as the clock f 1 output pin. p4 3 Cp4 7 function as i/o ports with the same functions as p0. port p5 is an 8-bit i/o port with the same function as p0. these pins can be programmed as i/o pins for timers a0Ca3. port p6 is an 8-bit i/o port with the same function as p0. these pins can be programmed as i/o pins for timer a4, input pins for external interrupt and input pins for timers b0Cb2. port p7 is an 8-bit i/o port with the same function as p0. these pins can be programmed as input pins for a-d converter. port p8 is an 8-bit i/o port with the same function as p0. these pins can be programmed as i/o pins for serial i/o. name i/o port p4 i/o port p5 i/o port p6 i/o port p7 i/o port p8 input/output i/o input input i/o input input output i/o i/o i/o i/o i/o
description 7751 group users manual 1C8 1.4 block diagram figure 1.4.1 shows the m37751 block diagram. 1.4 block diagram fig. 1.4.1 m37751 block diagram enable output x in x out e reset input reset reference voltage input v ref clock generating circuit data buffer db l (8) instruction queue buffer q 2 (8) data bank register dt (8) progtamu counter pc (16) incrementer/decrementer (24) program bank register pg (8) input buffer register ib (16) direct page register dpr (16) stack pointer s (16) index register x (16) arithmetic logic unit (16) accumulator a (16) instruction register (8) data bus (even) input/output port p0 watchdog timer cnvss byte external data bus width selection input timer b1 (16) timer b2 (16) p0 (8) timer b0 (16) timer a1 (16) timer a2 (16) timer a3 (16) timer a4 (16) timer a0 (16) rom 48 kbytes ram 2048 bytes uart1 (9) uart0 (9) av ss (0v) av cc central processing unit (cpu) incrementer (24) program address register pa (24) data address register da (24) address bus bus interface unit (biu) (0v) v ss v cc processor status register ps (11) a-d converter (10) clock input clock output accumulator b (16) index register y (16) instruction queue buffer q 1 (8) instruction queue buffer q 0 (8) data buffer db h (8) data bus (odd) p1 (8) input/output port p1 p2 (8) input/output port p2 p3 (4) input/output port p3 p4 (8) input/output port p4 p5 (8) input/output port p5 p6 (8) input/output port p6 p7 (8) input/output port p7 p8 (8) input/output port p8
chapter 2 central processing unit (cpu) 2.1 central processing unit 2.2 bus interface unit 2.3 access space 2.4 memory assignment 2.5 processor modes
central processing unit (cpu) 2.1 central processing unit 2C2 7751 group users manual 2.1 central processing unit the cpu (central processing unit) has the ten registers as shown in figure 2.1.1. fig. 2.1.1 cpu registers structure b0 b7 b8 b15 a h a l b0 b7 b8 b15 b h b l b0 b7 b8 b15 x h x l b0 b7 b8 b15 y h y l b0 b7 b8 b15 s h s l b0 b7 b8 b15 b7 b0 b8 b23 b16 b15 b7 b0 pc h pc l pg b0 b7 dt b0 b7 b8 b15 b0 b1 b2 b3 b4 b5 b6 b7 b8 b10 00000 c z i d x m v n ipl accumulator a (a) accumulator b (b) index register x (x) index register y (y) stack pointer (s) data bank register (dt) program counter (pc) program bank register (pg) direct page register (dpr) processor status register (ps) processor interrupt priority level carry flag zero flag interrupt disable flag index register length flag decimal mode flag data length flag overflow flag negative flag dpr l dpr h ps l ps h b9 b15
7751 group users manual 2.1 central processing unit central processing unit (cpu) 2C3 2.1.1 accumulator (acc) accumulators a and b are available. (1) accumulator a (a) accumulator a is the main register of the microcomputer. the transaction of data such as calculation, data transfer, and input/output are performed mainly through accumulator a. it consists of 16 bits, and the low-order 8 bits can also be used separately. the data length flag (m) determines whether the register is used as a 16-bit register or as an 8-bit register. flag m is a part of the processor status register which is described later. when an 8-bit register is selected, only the low-order 8 bits of accumulator a are used and the contents of the high-order 8 bits is unchanged. (2) accumulator b (b) accumulator b is a 16-bit register with the same function as accumulator a. accumulator b can be used instead of accumulator a. the use of accumulator b, however except for some instructions, requires more instruction bytes and execution cycles than that of accumulator a. accumulator b is also controlled by the data length flag (m) just as in accumulator a. 2.1.2 index register x (x) index register x consists of 16 bits and the low-order 8 bits can also be used separately. the index register length flag (x) determines whether the register is used as a 16-bit register or as an 8-bit register. flag x is a part of the processor status register which is described later. when an 8-bit register is selected, only the low-order 8 bits of index register x are used and the contents of the high-order 8 bits is unchanged. in an addressing mode in which index register x is used as an index register, the address obtained by adding the contents of this register to the operands contents is accessed. in the mvp or mvn instruction, a block transfer instruction, the contents of index register x indicate the low-order 16 bits of the source address. the third byte of the instruction is the high-order 8 bits of the source address. in the rmpa instruction, a repeat multiply and accumulate instruction, the contents of index register x indicate the low-order 16 bits of address in which multiplicands are stored. note: refer to 7751 series software manual for addressing modes. 2.1.3 index register y (y) index register y is a 16-bit register with the same function as index register x. just as in index register x, the index register length flag (x) determines whether this register is used as a 16-bit register or as an 8-bit register. in the mvp or mvn instruction, a block transfer instruction, the contents of index register y indicate the low-order 16 bits of the destination address. the second byte of the instruction is the high-order 8 bits of the destination address. in the rmpa instruction, a repeat multiply and accumulate instruction, the contents of index register y indicate the low-order 16 bits of address in which multipliers are stored.
central processing unit (cpu) 2.1 central processing unit 2C4 7751 group users manual 2.1.4 stack pointer (s) the stack pointer (s) is a 16-bit register. it is used for a subroutine call or an interrupt. it is also used when addressing modes using the stack are executed. the contents of s indicate an address (stack area) for storing registers during subroutine calls and interrupts. bank 0 16 is specified for the stack area. (refer to 2.1.6 program bank register (pg). ) when an interrupt request is accepted, the microcomputer stores the contents of the program bank register (pg) at the address indicated by the contents of s and decrements the contents of s by 1. then the contents of the program counter (pc) and the processor status register (ps) are stored. the contents of s after accepting an interrupt request is equal to the contents of s decremented by 5 before the accepting of the interrupt request. (refer to figure 2.1.2.) when completing the process in the interrupt routine and returning to the original routine, the contents of registers stored in the stack area are restored into the original registers in the reverse sequence (ps ? pc ? pg) by executing the rti instruction. the contents of s is returned to the state before accepting an interrupt request. the same operation is performed during a subroutine call, however, the contents of ps is not automatically stored. (the contents of pg may not be stored. this depends on the addressing mode.) the user should store registers other than those described above with software when the user needs them during interrupts or subroutine calls. additionally, initialize s at the beginning of the program because its contents are undefined at reset. the stack area changes when subroutines are nested or when multiple interrupt requests are accepted. therefore, make sure of the subroutines nesting depth not to destroy the necessary data. note: refer to 7751 series software manual for addressing modes. fig. 2.1.2 stored registers of the stack area l s is the initial address that the stack pointer (s) indicates at accepting an interrupt request. the ss contents become sC5 after storing the above registers. address sC4 sC3 sC2 sC1 s stack area sC5 processor status registers low-order byte (ps l ) processor status registers high-order byte (ps h ) program counters low-order byte (pc l ) program counters high-order byte (pc h ) program bank register (pg)
7751 group users manual 2.1 central processing unit central processing unit (cpu) 2C5 2.1.5 program counter (pc) the program counter is a 16-bit counter that indicates the low-order 16 bits of the address (24 bits) at which an instruction to be executed next (in other words, an instruction to be read out from an instruction queue buffer next) is stored. the contents of the high-order program counter (pc h ) become ff 16 , and the low-order program counter (pc l ) becomes fe 16 at reset. the contents of the program counter becomes the contents of the resets vector address (addresses fffe 16 , ffff 16 ) immediately after reset. figure 2.1.3 shows the program counter and the program bank register. fig. 2.1.3 program counter and program bank register 2.1.6 program bank register (pg) the program bank register is an 8-bit register. this register indicates the high-order 8 bits (bank) of the address (24 bits) at which an instruction to be executed next (in other words, an instruction to be read out from an instruction queue buffer next) is stored. these 8 bits are called bank. when a carry occurs after adding the contents of the program counter or adding the offset value to the contents of the program counter in the branch instruction and others, the contents of the program bank register is automatically incremented by 1. when a borrow occurs after subtracting the contents of the program counter, the contents of the program bank register is automatically decremented by 1. accordingly, there is no need to consider bank boundaries in programming, usually. in the single-chip mode, make sure to prevent the program bank register from being set to the value other than 00 16 by executing the branch instructions and others. it is because the access space of the single- chip mode is the internal area within the bank 0 16 . this register is cleared to 00 16 at reset. pc h pc l b7 b0 b15 b8 b7 b0 (b16) (b23) pg
central processing unit (cpu) 2.1 central processing unit 2C6 7751 group users manual 2.1.7 data bank register (dt) the data bank register is an 8-bit register. in the following addressing modes using the data bank register, the contents of this register is used as the high-order 8 bits (bank) of a 24-bit address to be accessed. use the ldt instruction to set a value to this register. in the single-chip mode, make sure to fix this register to 00 16 . it is because the access space of the single-chip mode is the internal area within the bank 0 16 . this register is cleared to 00 16 at reset. l addressing modes using data bank register ?direct indirect ?direct indexed x indirect ?direct indirect indexed y ?absolute ?absolute bit ?absolute indexed x ?absolute indexed y ?absolute bit relative ?stack pointer relative indirect indexed y ?multiplied accumulation 2.1.8 direct page register (dpr) the direct page register is a 16-bit register. the contents of this register indicate the direct page area which is allocated in bank 0 16 or in the space across banks 0 16 and 1 16 . the following addressing modes use the direct page register. the contents of the direct page register indicate the base address (the lowest address) of the direct page area. the space which extends to 256 bytes above that address is specified as a direct page. the direct page register can contain a value from 0000 16 to ffff 16 . when it contains a value equal to or more than ff01 16 , the direct page area spans the space across banks 0 16 and 1 16 . when the contents of low-order 8 bits of the direct page register is 00 16 , the number of cycles required to generate an address is 1 cycle smaller than the number when its contents are not 00 16 . accordingly, the access efficiency can be enhanced in this case. this register is cleared to 0000 16 at reset. figure 2.1.4 shows a setting example of the direct page area. l addressing modes using direct page register ?direct ?direct bit ?direct indexed x ?direct indexed y ?direct indirect ?direct indexed x indirect ?direct indirect indexed y ?direct indirect long ?direct indirect long indexed y ?direct bit relative
7751 group users manual 2.1 central processing unit central processing unit (cpu) 2C7 direct page area when dpr = 0000 16 direct page area when dpr = 0123 16 (note 1) direct page area when dpr = ff10 16 (note 2) bank 0 16 bank 1 16 0 16 ff 16 123 16 222 16 ff10 16 1000f 16 0 16 ffff 16 10000 16 notes 1 : the number of cycles required to generate an address is 1 cycle smaller when the low-order 8 bits of the dpr are 00 16 . 2: the direct page area spans the space across banks 0 16 and 1 16 when the dpr is ff01 16 or more. fig. 2.1.4 setting example of direct page area
central processing unit (cpu) 2.1 central processing unit 2C8 7751 group users manual 2.1.9 processor status register (ps) the processor status register is an 11-bit register. figure 2.1.5 shows the structure of the processor status register. b15 b8 b7 b0 b1 b2 b3 b4 b5 b6 b14 b9 b10 b11 b12 b13 z i d x m v 0 ipl 0 0 0 processor status register (ps) note : fix bits 11C15 to 0. fig. 2.1.5 processor status register structure (1) bit 0: carry flag (c) it retains a carry or a borrow generated in the arithmetic and logic unit (alu) during an arithmetic operation. this flag is also affected by shift and rotate instructions. when the bcc or bcs instruction is executed, this flags contents determine whether the program causes a branch or not. use the sec or sep instruction to set this flag to 1, and use the clc or clp instruction to clear it to 0. (2) bit 1: zero flag (z) it is set to 1 when a result of an arithmetic operation or data transfer is 0, and cleared to 0 when otherwise. when the bne or beq instruction is executed, this flags contents determine whether the program causes a branch or not. use the sep instruction to set this flag to 1, and use the clp instruction to clear it to 0. note: this flag is invalid in the decimal mode addition (the adc instruction). (3) bit 2: interrupt disable flag (i) it disables all maskable interrupts (interrupts other than watchdog timer, the brk instruction, and zero division). interrupts are disabled when this flag is 1. when an interrupt request is accepted, this flag is automatically set to 1 to avoid multiple interrupts. use the sei or sep instruction to set this flag to 1, and use the cli or clp instruction to clear it to 0. this flag is set to 1 at reset. (4) bit 3: decimal mode flag (d) it determines whether addition and subtraction are performed in binary or decimal. binary arithmetic is performed when this flag is 0. when it is 1, decimal arithmetic is performed with each word treated as two or four digits decimal (determined by the data length flag). decimal adjust is automatically performed. decimal operation is possible only with the adc and sbc instructions. use the sep instruction to set this flag to 1, and use the clp instruction to clear it to 0. this flag is cleared to 0 at reset. (5) bit 4: index register length flag (x) it determines whether each of index register x and index register y is used as a 16-bit register or an 8-bit register. that register is used as a 16-bit register when this flag is 0, and as an 8-bit register when it is 1. use the sep instruction to set this flag to 1, and use the clp instruction to clear it to 0. this flag is cleared to 0 at reset. note: when transferring data between registers which are different in bit length, the data is transferred with the length of the destination register, but except for the txa , tya , txb , tyb , and txs instructions. refer to 7751 series software manual for details. n c 0
7751 group users manual 2.1 central processing unit central processing unit (cpu) 2C9 (6) bit 5: data length flag (m) it determines whether to use a data as a 16-bit unit or as an 8-bit unit. a data is treated as a 16- bit unit when this flag is 0, and as an 8-bit unit when it is 1. use the sem or sep instruction to set this flag to 1, and use the clm or clp instruction to clear it to 0. this flag is cleared to 0 at reset. note: when transferring data between registers which are different in bit length, the data is transferred with the length of the destination register, but except for the txa , tya , txb , tyb , and txs instructions. refer to 7751 series software manual for details. (7) bit 6: overflow flag (v) it is used when adding or subtracting with a word regarded as signed binary. when the data length flag (m) is 0, the overflow flag is set to 1 when the result of addition or subtraction exceeds the range between C32768 and +32767, and cleared to 0 in all other cases. when the data length flag (m) is 1, the overflow flag is set to 1 when the result of addition or subtraction exceeds the range between C128 and +127, and cleared to 0 in all other cases. the overflow flag is also set to 1 when a result of division exceeds the register length to be stored in the div or divs instruction, a division instruction with unsigned or signed; and when a result of addition exceeds the range between C2147483648 and +2147483647 in the rmpa instruction, a repeat multiply and accumulate instruction. when the bvc or bvs instruction is executed, this flags contents determine whether the program causes a branch or not. use the sep instruction to set this flag to 1, and use the clv or clp instruction to clear it to 0. note: this flag is invalid in the decimal mode. (8) bit 7: negative flag (n) it is set to 1 when a result of arithmetic operation or data transfer is negative. (bit 15 of the result is 1 when the data length flag (m) is 0, or bit 7 of the result is 1 when the data length flag (m) is 1.) it is cleared to 0 in all other cases. when the bpl or bmi instruction is executed, this flag determines whether the program causes a branch or not. use the sep instruction to set this flag to 1, and use the clp instruction to clear it to 0. note: this flag is invalid in the decimal mode. (9) bits 10 to 8: processor interrupt priority level (ipl) these three bits can determine the processor interrupt priority level to one of levels 0 to 7. the interrupt is enabled when the interrupt priority level of a required interrupt, which is set in each interrupt control register, is higher than ipl. when an interrupt request is accepted, ipl is stored in the stack area, and ipl is replaced by the interrupt priority level of the accepted interrupt request. there are no instruction to directly set or clear the bits of ipl. ipl can be changed by storing the new ipl into the stack area and updating the processor status register with the pul or plp instruction. the contents of ipl is cleared to 000 2 at reset.
central processing unit (cpu) 7751 group users manual 2C10 2.2 bus interface unit 2.2 bus interface unit a bus interface unit (biu) is built-in between the central processing unit (cpu) and memory?i/o devices. bius function and operation are described below. when externally connecting devices, refer to chapter 12. connection with external devices. 2.2.1 overview transfer operation between the cpu and memory?i/o devices is always performed via the biu. figure 2.2.1 shows the bus and bus interface unit (biu). ? the biu reads an instruction from the memory before the cpu executes it. ? when the cpu reads data from the memory?i/o device, the cpu first specifies the address from which data is read to the biu. the biu reads data from the specified address and passes it to the cpu. ? when the cpu writes data to the memory?i/o device, the cpu first specifies the address to which data is written to the biu and write data. the biu writes the data to the specified address. to perform the above operations ? to ? , the biu inputs and outputs the control signals, and control the bus.
central processing unit (cpu) 7751 group users manual 2C11 2.2 bus interface unit fig. 2.2.1 bus and bus interface unit (biu) m37751 internal bus d 8 to d 15 central processing unit (cpu) sfr : special function register notes 1: the cpu bus, internal bus, and external bus are independent of one another. 2: refer to chapter 12. connection with external devices about control signals of the external bus. internal bus a 0 to a 23 external device internal control signal cpu bus internal bus internal bus d 0 to d 7 internal memory internal peripheral device (sfr) external bus a 0 to a 7 a 16 /d 0 to a 23 /d 7 control signals bus interface unit (biu) a 8 /d 8 to a 15 /d 15 bus conversion circuit
central processing unit (cpu) 7751 group users manual 2C12 2.2 bus interface unit 2.2.2 functions of bus interface unit (biu) the bus interface unit (biu) consists of four registers shown in figure 2.2.2. table 2.2.1 lists the functions of each register. program address register instruction queue buffer data address register data buffer pa da q 0 q 1 q 2 db h db l b23 b0 b0 b0 b0 b23 b15 b7 table 2.2.1 functions of each register functions indicates the storage address for the instruction which is next taken into the instruction queue buffer. temporarily stores the instruction which has been taken in. indicates the address for the data which is next read from or written to. temporarily stores the data which is read from the memory?i/o device by the biu or which is written to the memory?i/o device by the cpu. name program address register instruction queue buffer data address register data buffer fig. 2.2.2 register structure of bus interface unit (biu)
central processing unit (cpu) 7751 group users manual 2C13 2.2 bus interface unit the cpu and the bus send or receive data via biu because each operates based on different clocks (note) . the biu allows the cpu to operate at high speed without waiting for access to the memory ? i/o devices that require a long access time. the bius functions are described bellow. note: the cpu operates based on f cpu . the period of f cpu is normally the same as that of f . the internal _ bus operates based on the e signal. the period of the e signal is twice that of f at a minimum. (1) reading out instruction (instruction prefetch) when the cpu does not require to read or write data, that is, when the bus is not in use, the biu reads instructions from the memory and stores them in the instruction queue buffer. this is called instruction prefetch. the cpu reads instructions from the instruction queue buffer and executes them, so that the cpu can operate at high speed without waiting for access to the memory which requires a long access time. when the instruction queue buffer becomes empty or contains only 1 byte of an instruction, the biu performs instruction prefetch. the instruction queue buffer can store instructions up to 3 bytes. the contents of the instruction queue buffer is initialized when a branch or jump instruction is executed, and the biu reads a new instruction from the destination address. when instructions in the instruction queue buffer are insufficient for the cpus needs, the biu extends the pulse duration of clock f cpu in order to keep the cpu waiting until the biu fetches the required number of instructions or more. (2) reading data from memory?i/o device the cpu specifies the storage address of data to be read to the bius data address register, and requires data. the cpu waits until data is ready in the biu. the biu outputs the address received from the cpu onto the address bus, reads contents at the specified address, and takes it into the data buffer. the cpu continues processing, using data in the data buffer. however, if the biu uses the bus for instruction prefetch when the cpu requires to read data, the biu keeps the cpu waiting. (3) writing data to memory?i/o device the cpu specifies the address of data to be written to the bius data address register. then, the cpu writes data into the data buffer. the biu outputs the address received from the cpu onto the address bus and writes data in the data buffer into the specified address. the cpu advances to the next processing without waiting for completion of bius write operation. however, if the biu uses the bus for instruction prefetch when the cpu requires to write data, the biu keeps the cpu waiting. _
central processing unit (cpu) 7751 group users manual 2C14 2.2 bus interface unit (4) bus control to perform the above operations (1) to (3), the biu inputs and outputs the control signals, and controls the address bus and the data bus. the cycle in which the biu controls the bus and accesses the memory?i/o device is called the bus cycle. table 2.2.2 shows the bus cycle at accessing the internal area. refer to chapter 12. connection with external devices about the bus cycle at accessing the external devices. table 2.2.2 bus cycle at accessing internal area ram rom sfr in low-speed running (f(x in ) 25 mhz) e internal address bus internal data bus address data 1 bus cycle = 3 1 bus cycle = 2 address internal address bus internal data bus data e internal address bus internal data bus 1 bus cycle = 2 address data e in high-speed running (f(x in ) 40 mhz)
central processing unit (cpu) 7751 group users manual 2C15 2.2 bus interface unit 2.2.3 operation of bus interface unit (biu) figure 2.2.3 shows the basic operating waveforms of the bus interface unit (biu). about signals which are input/output externally when accessing external devices, refer to chapter 12. connection with external devices. (1) when fetching instructions into the instruction queue buffer ? when the instruction which is next fetched is located at an even address, the biu fetches 2 bytes at a time with the timing of waveform (a). however, when accessing an external device which is connected with the 8-bit external data bus width (byte = h), only 1 byte is fetched. ? when the instruction which is next fetched is located at an odd address, the biu fetches only 1 byte with the timing of waveform (a). the contents at the even address are not taken. (2) when reading or writing data to and from the memory?i/o device ? when accessing a 16-bit data which begins at an even address, waveform (a) is applied. the 16 bits of data are accessed at a time. ? when accessing a 16-bit data which begins at an odd address, waveform (b) is applied. the 16 bits of data are accessed separately in 2 operations, 8 bits at a time. invalid data is not fetched into the data buffer. ? when accessing an 8-bit data at an even address, waveform (a) is applied. the data at the odd address is not fetched into the data buffer. when accessing an 8-bit data at an odd address, waveform (a) is applied. the data at the even address is not fetched into the data buffer. for instructions that are affected by the data length flag (m) and the index register length flag (x), operation ? or ? is applied when flag m or x = 0; operation ? or is applied when flag m or x = 1.
central processing unit (cpu) 7751 group users manual 2C16 2.2 bus interface unit fig. 2.2.3 basic operating waveforms of bus interface unit (biu) address (a) data (even address) data (odd address) e internal address bus (a 0 to a 23 ) internal data bus (d 0 to d 7 ) internal data bus (d 8 to d 15 ) (b) address (odd address) address (even address) data (even address) data (odd address) invalid data invalid data internal address bus (a 0 to a 23 ) internal data bus (d 0 to d 7 ) internal data bus (d 8 to d 15 ) e
central processing unit (cpu) 7751 group users manual 2C17 2.3 access space 2.3 access space figure 2.3.1 shows the m37751s access space. by combination of the program counter (pc), which is 16 bits of structure, and the program bank register (pg), a 16-mbyte space from addresses 0 16 to ffffff 16 can be accessed. for details about access of an external area, refer to chapter 12. connection with external devices. the memory and i/o devices are allocated in the same access space. accordingly, it is possible to perform transfer and arithmetic operations using the same instructions without discrimination of the memory from i/o devices. fig. 2.3.1 m37751s access space : indicates the memory assignment of the internal areas. : indicates that nothing is assigned. note : memory assignment of internal area varies according to the type of microcomputer. this figure shows the case of the m37751m6c-xxxfp. refer to appendix 1. memory assignment for other products. sfr : special function register 000000 16 000080 16 00ffff 16 010000 16 fe0000 16 ff0000 16 ffffff 16 sfr area internal ram area bank 0 16 internal rom area 020000 16 00087f 16 00007f 16 bank 1 16 bank ff 16 bank fe 16 004000 16
7751 group users manual central processing unit (cpu) 2C18 2.3.1 banks the access space is divided in units of 64 kbytes. this unit is called bank. the high-order 8 bits of address (24 bits) indicate a bank, which is specified by the program bank register (pg) or data bank register (dt). each bank can be accessed efficiently by using an addressing mode that uses the data bank register (dt). if the program counter (pc) overflows at a bank boundary, the contents of the program bank register (pg) is incremented by 1. if a borrow occurs in the program counter (pc) as a result of subtraction, the contents of the program bank register (pg) is decremented by 1. normally, accordingly, the user can program without concern for bank boundaries. sfr (special function register), internal ram, and internal rom are assigned in bank 0 16 . for details, refer to section 2.4 memory assignment. 2.3.2 direct page a 256-byte space specified by the direct page register (dpr) is called direct page. a direct page is specified by setting the base address (the lowest address) of the area to be specified as a direct page into the direct page register (dpr). by using a direct page addressing mode, a direct page can be accessed with less instruction cycles than otherwise. note: refer also to section 2.1 central processing unit. 2.3 access space
central processing unit (cpu) 7751 group users manual 2C19 2.4 memory assignment 2.4 memory assignment this section describes the internal areas memory assignment. for more information about the external area, refer also to section 2.5 processor modes. 2.4.1 memory assignment in internal area sfr (special function register), internal ram, and internal rom are assigned in the internal area. figure 2.4.1 shows the internal areas memory assignment. (1) sfr area the registers for setting internal peripheral devices are assigned at addresses 0 16 to 7f 16 . this area is called sfr (special function register). figure 2.4.2 shows the sfr areas memory assignment. for each register in the sfr area, refer to each functional description in this manual. for the state of the sfr area immediately after a reset, refer to section 13.1.2 state of cpu, sfr area, and internal ram area. (2) internal ram area the m37751m6c-xxxfp (see note ) assigns the 2048-byte static ram at addresses 80 16 to 87f 16 . the internal ram area is used as a stack area, as well as an area to store data. accordingly, note that set the nesting depth of a subroutine and multiple interrupts level not to destroy the necessary data. (3) internal rom area the m37751m6c-xxxfp (see note ) assigns the 48-kbyte mask ram at addresses 4000 16 to ffff 16 . its addresses ffd6 16 to ffff 16 are the vector addresses, which are called the interrupt vector table, for reset and interrupts. in the microprocessor mode where use of the internal rom area is inhibited, assign a rom at addresses ffd6 16 to ffff 16 . note : refer to appendix 1. memory assignment for other products.
7751 group users manual central processing unit (cpu) 2C20 2.4 memory assignment timer a0 l h l h l h l h l h l h l h h l h timer a4 l h l timer a3 h timer a2 l h timer a1 l h l h l h l h l h l h timer b2 l h timer b1 l h timer b0 l h a-d conversion uart1 transmit uart1 receive uart0 transmit uart0 receive int 2 int 1 int 0 watchdog timer dbc (note 1) brk instruction zero divide reset ffd6 16 ffd8 16 ffda 16 ffdc 16 ffde 16 ffe0 16 ffe2 16 ffe8 16 ffec 16 ffe4 16 ffe6 16 ffea 16 ffee 16 fff0 16 fff2 16 fff4 16 fff6 16 fff8 16 fffa 16 fffc 16 fffe 16 interrupt vector table 00007f 16 000000 16 000080 16 00ffff 16 00ffd6 16 internal ram area refer to figure 2.4.2. l notes 1: dbc is an interrupt only for debugging; do not use this interrupt. 2: access to the internal rom area is disabled in the microprocessor mode. (refer to section 2.5 processor modes. ) 3: memory assignment of internal area varies according to the type of microcomputer. refer to appendix 1. memory assignment for other products. internal rom area sfr area 004000 16 00087f 16 m37751m6c-xxxfp : the internal memory is not assigned. fig. 2.4.1 internal areas memory assignment
central processing unit (cpu) 7751 group users manual 2C21 2.4 memory assignment fig. 2.4.2 sfr areas memory map 0 16 1 16 2 16 3 16 4 16 5 16 6 16 7 16 8 16 9 16 10 16 11 16 12 16 13 16 14 16 15 16 16 16 17 16 18 16 19 16 1a 16 1b 16 1c 16 1d 16 1e 16 1f 16 20 16 21 16 22 16 23 16 24 16 25 16 26 16 27 16 28 16 29 16 2a 16 2b 16 2c 16 2d 16 2e 16 2f 16 30 16 31 16 32 16 33 16 34 16 35 16 36 16 37 16 38 16 39 16 3a 16 3b 16 3c 16 3d 16 3e 16 3f 16 b 16 c 16 d 16 e 16 f 16 a 16 address 50 16 51 16 52 16 53 16 54 16 55 16 56 16 57 16 58 16 59 16 5a 16 5b 16 5c 16 5d 16 5e 16 5f 16 60 16 61 16 62 16 63 16 64 16 65 16 66 16 67 16 68 16 69 16 6a 16 6b 16 6c 16 6d 16 6e 16 6f 16 70 16 71 16 72 16 73 16 74 16 75 16 76 16 77 16 78 16 79 16 7a 16 7b 16 7c 16 7d 16 7e 16 7f 16 address 4e 16 4f 16 4c 16 4d 16 4a 16 4b 16 48 16 49 16 46 16 47 16 44 16 45 16 42 16 43 16 40 16 41 16 port p8 direction register timer a1 register timer a4 register timer a2 register timer a3 register timer b0 register timer b1 register timer b2 register count start register one-shot start register up-down register timer a0 register timer a0 mode register timer a1 mode register timer a2 mode register timer a3 mode register timer a4 mode register timer b0 mode register timer b1 mode register timer b2 mode register processor mode register 0 watchdog timer register watchdog timer frequency select register a-d conversion interrupt control register uart0 receive interrupt control register uart1 receive interrupt control register timer a0 interrupt control register timer a1 interrupt control register timer a2 interrupt control register timer a3 interrupt control register timer a4 interrupt control register timer b0 interrupt control register timer b1 interrupt control register timer b2 interrupt control register port p4 register port p5 register port p4 direction register port p5 direction register port p6 register port p7 register port p6 direction register port p7 direction register port p8 register a-d control register 0 uart0 transmit/receive mode register uart0 baud rate register (brg0) uart0 transmit/receive control register 0 uart0 transmit/receive control register 1 uart0 transmit buffer register uart1 transmit/receive control register 0 uart1 transmit/receive mode register uart1 baud rate register (brg1) uart1 transmit/receive control register 1 uart0 receive buffer register uart1 transmit buffer register uart1 receive buffer register a-d control register 1 a-d register 0 a-d register 1 a-d register 2 a-d register 3 a-d register 4 a-d register 5 uart0 transmit interrupt control register uart1 transmit interrupt control register int 0 interrupt control register int 1 interrupt control register int 2 interrupt control register a-d register 6 a-d register 7 port p0 register port p1 register port p0 direction register port p1 direction register port p2 register port p3 register port p2 direction register port p3 direction register processor mode register 1
7751 group users manual central processing unit (cpu) 2C22 2.5 processor modes the m37751 can operate in 3 processor modes: single-chip mode, memory expansion mode, and microprocessor mode. some pins functions, memory assignment, and access space vary according to the processor modes. this section describes the differences between the processor modes. figure 2.5.1 shows a memory assignment in each processor mode. 2.5 processor modes fig. 2.5.1 memory assignment in each processor mode for m37751m6c-xxxfp 000000 16 00ffff 16 000080 16 sfr area internal rom area single-chip mode internal ram area sfr area memory expansion mode 010000 16 ffffff 16 sfr area microprocessor mode not used internal ram area internal ram area internal rom area 000002 16 000009 16 (note 1) : external area; accessing this area make it possible to access external connected devices. notes 1: addresses 2 16 to 9 16 become a external area in the memory expansion mode and microprocessor mode. 2: refer to appendix 1. memory assignment for products other than m37751m6cCxxxfp. 00087f 16 004000 16 000880 16 003fff 16 memory expansion mode microprocessor mode
central processing unit (cpu) 7751 group users manual 2C23 2.5.1 single-chip mode use this mode when not using external devices. in this mode, ports p0 to p8 function as programmable i/o ports (when using an internal peripheral device, they function as its i/o pins). in the single-chip mode, only the internal area (sfr, internal ram, and internal rom) can be accessed. 2.5.2 memory expansion and microprocessor modes use these modes when connecting devices externally. in these modes, an external device can be connected to any required location in the 16-mbyte access space. for access to external devices, refer to chapter 12. connection with external devices. the memory expansion and microprocessor modes have the same functions except for the following: ?in the microprocessor mode, access to the internal rom area is disabled by force, and the internal rom area is handled as an external area. ?in the microprocessor mode, port p4 2 always functions as the clock f 1 output pin. in the memory expansion and microprocessor modes, p0 to p3, p4 0 , and p4 1 function as the i/o pins for the signals required for accessing external devices. consequently, these pins cannot be used as programmable i/o ports. if an external device is connected with an area with which the internal area overlaps, when this overlapping area is read, data in the internal area is taken in the cpu, but data in the external area is not taken in. if data is written to an overlapping area, the data is written to the internal area, and a signal is output externally at the same timing as writing to the internal area. figure 2.5.2 shows a pin configuration in each processor mode. table 2.5.1 lists the functions of p0 to p4 in each processor mode. for the function of each pin, refer to section 1.3 pin description, chapter 3. input/output pins, and chapter 12. connection with external devices. 2.5 processor modes
7751 group users manual central processing unit (cpu) 2C24 2.5 processor modes p8 4 /cts 1 /rts 1 p8 5 /clk 1 p8 6 /r x d 1 p8 7 /t x d 1 p7 0 /an 0 p6 7 /tb2 in p6 6 /tb1 in p6 5 /tb0 in p6 4 /int 2 p6 3 /int 1 p6 2 /int 0 p6 1 /ta4 in p6 0 /ta4 out p5 7 /ta3 in p5 6 /ta3 out p5 5 /ta2 in p5 4 /ta2 out p5 3 /ta1 in p5 2 /ta1 out p5 1 /ta0 in p5 0 /ta0 out 25 27 26 28 34 29 30 31 32 33 35 36 37 38 39 40 1 4 3 2 5 p2 4 p2 5 p2 6 p2 7 p3 0 p3 1 p3 2 p3 3 v ss e x out x in reset cnv ss ] 1 byte p4 0 p8 3 /t x d 0 p8 2 /r x d 0 p8 1 /clk 0 p8 0 /cts 0 /rts 0 v cc av cc v ref av ss v ss p7 7 /an 7 /ad trg p7 6 /an 6 p7 5 /an 5 p7 4 /an 4 p7 3 /an 3 p7 2 /an 2 p7 1 /an 1 6 7 8 9 1011121314151617181920 21 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 80 79 78 77 76 75 74 73 72 71 69 68 67 66 65 70 p1 3 p1 4 p1 5 p1 6 p1 7 p2 0 p2 1 p2 2 p2 3 43 42 41 m37751m6cCxxxfp 22 23 24 p4 1 p4 7 p4 6 p4 5 p4 4 p4 3 p4 2 / f 1 p0 0 p0 1 p0 2 p0 3 p0 4 p0 5 p0 6 p0 7 p1 0 p1 1 p1 2 p7 0 /an 0 p6 7 /tb2 in p6 6 /tb1 in p6 5 /tb0 in p6 4 /int 2 p6 3 /int 1 p6 2 /int 0 p6 1 /ta4 in p6 0 /ta4 out p5 7 /ta3 in p5 6 /ta3 out p5 5 /ta2 in p5 4 /ta2 out p5 3 /ta1 in p5 2 /ta1 out p5 1 /ta0 in p5 0 /ta0 out 25 27 26 28 34 29 30 31 32 33 35 36 37 38 39 40 1 4 3 2 5 a 20 /d 4 a 21 /d 5 a 22 /d 6 a 23 /d 7 r/w bhe ale hlda v ss e x out x in reset cnv ss byte hold 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 80 79 78 77 76 75 74 73 72 71 69 68 67 66 65 70 a 11 /d 11 a 12 /d 12 a 13 /d 13 a 14 /d 14 a 15 /d 15 a 16 /d 0 a 17 /d 1 a 18 /d 2 a 19 /d 3 43 42 41 m37751m6cCxxxfp 22 23 24 rdy p4 7 p4 6 p4 5 p4 4 p4 3 ] 2 p4 2 / f 1 p8 4 /cts 1 /rts 1 p8 5 /clk 1 p8 6 /r x d 1 p8 7 /t x d 1 a 0 a 1 a 2 a 3 a 4 a 5 a 6 a 7 a 8 /d 8 a 9 /d 9 a 10 /d 10 p8 3 /t x d 0 p8 2 /r x d 0 p8 1 /clk 0 p8 0 /cts 0 /rts 0 v cc av cc v ref av ss v ss p7 7 /an 7 /ad trg p7 6 /an 6 p7 5 /an 5 p7 4 /an 4 p7 3 /an 3 p7 2 /an 2 p7 1 /an 1 ] 1 connect this pin to vss pin in the single-chip mode. : these pins have different functions between the single-chip and the memory expansion/micropro- cessor modes. ] 2 this pin functions as f 1 in the microprocessor mode. : these pins have different functions between the single-chip and the memory expansion/micropro- cessor modes. l memory expansion/microprocessor mode l single-chip mode fig. 2.5.2 pin configuration in each processor mode (top view)
central processing unit (cpu) 7751 group users manual 2C25 table 2.5.1 functions of ports p0 to p4 in each processor mode 2.5 processor modes p0 pins p1 processor modes p4 p2 p: functions as a programmable i/o port. (note 2) p p: functions as a programmable i/o port. p single-chip mode p: functions as a programmable i/o port. p p3 ? when external data bus width is 16 bits (byte = l) memory expansion/microprocessor mode d(even) d (even): data at even address d(odd) d (odd): data at odd address a 0 C a 7 (note 1) hlda p3 1 p3 2 p3 0 p3 3 ale bhe notes 1: p4 2 also functions as the clock 1 output pin. (refer to chapter 12. connection with external devices. ) 2: p4 2 functions as a programmable i/o port in the memory expansion mode, and that functions as the clock 1 output pin by software selection. (refer to chapter 12. connection with external devices. ) 3: this table lists a switch of pins functions by switching the processor mode. refer to the following section about the input/output timing of each signal: ? chapter 12. connection with external devices. ? chapter 15. electrical characteristics. p: functions as a programmable i/o port. p p: functions as a programmable i/o port. p ? when external data bus width is 8 bits (byte = h) a 8 C a 15 a 8 C a 15 ? when external data bus width is 16 bits (byte = l) ? when external data bus width is 8 bits (byte = h) a 16 C a 23 a 16 C a 23 r/w p: functions as a programmable i/o port. rdy hold p4 1 p4 2 p4 0 1 p4 3 C p4 7 p d d : data
7751 group users manual central processing unit (cpu) 2C26 2.5.3 setting processor modes the voltage supplied to the cnvss pin and the processor mode bits (bits 1 and 0 at address 5e 16 ) set the processor mode. l when vss level is supplied to cnvss pin after a reset, the microcomputer starts operating in the single-chip mode. the processor mode is switched by the processor mode bits after the microcomputer starts operating. when the processor mode bits are set to 01 2 , the microcomputer enters the memory expansion mode; when these bits are set to 10 2 , the microcomputer enters the microprocessor mode. _ the processor mode is switched at the rising edge of signal e after writing to the processor mode bits. figure 2.5.3 shows the timing when pin functions are switched by switching the processor mode from the single-chip mode to the memory expansion or microprocessor mode with the processor mode bits. when the processor mode is switched during the program execution, the contents of the instruction queue buffer is not initialized. (refer to appendix 9. q & a. ) l when vcc level is supplied to cnvss pin after a reset, the microcomputer starts operating in the microprocessor mode. in this case, the microcomputer cannot operate in the other modes. (fix the processor mode bits to 10 2 .) table 2.5.2 lists the methods for setting processor modes. figure 2.5.4 shows the structure of processor mode register 0 (address 5e 16 ). 2.5 processor modes external address bus a 0 p0 0 e written to processor mode bits programmable i/o port p0 0 note: functions of pins p0 1 to p0 7 , p1 to p3, p4 0 to p4 2 are switched at the same timing shown above. function of pin p4 2 is, however, switched only when the processor mode is switched to the microprocessor mode. fig. 2.5.3 timing when pin functions are switched
central processing unit (cpu) 7751 group users manual 2C27 processor mode cnvss pin level processor mode bits b1 b0 single-chip mode vss (0 v) ( note 1 ) memory expansion mode vss (0 v) ( note 1 ) microprocessor mode vss (0 v) ( note 1 ) vcc (5 v) ( note 2 ) 2.5 processor modes notes 1: the microcomputer starts operating in the single-chip mode after a reset. the microcomputer can be switched to the other processor modes by setting the processor mode bits. 2: the microcomputer starts operating in the microprocessor mode after a reset. the microcomputer cannot operate in the other modes, so that fix the processor mode bits as follows: ?b1 = 1 and b0 = 0. table 2.5.2 methods for setting processor modes notes 1: while supplying the vcc level to the cnvss pin, this bit becomes 1 after a reset. (fixed to 1.) 2: this bit is ignored in the microprocessor mode. (it may be either 0 or 1.) bit bit name functions at reset rw 0 1 2 3 4 5 6 7 processor mode bits software reset bit interrupt priority detection time select bits clock f 1 output select bit (note 2) 0 0 0 0 0 0 : single-chip mode 0 1 : memory expansion mode 1 0 : microprocessor mode 1 1 : not selected the microcomputer is reset by writing 1 to this bit. the value is 0 at reading. 0 0 : 7 cycles of f 0 1 : 4 cycles of f 1 0 : 2 cycles of f 1 1 : not selected 0 : clock f 1 output disabled (p4 2 functions as a programmable i/o port.) 1 : clock f 1 output enabled (p4 2 functions as a clock f 1 out- put pin.) 0 0 b1 b0 b5 b4 processor mode register 0 (address 5e 16 ) (note 1) b1 b0 b2 b3 b4 b5 b6 b7 0 rw rw rw wo 0 rw 0 rw fix this bit to 0. rw rw : bits 7 to 2 are not used for setting of the processor mode. fix this bit to 0. 0 fig. 2.5.4 structure of processor mode register 0 0 0 0 1 10
7751 group users manual central processing unit (cpu) 2C28 2.5 processor modes [precautions when operating in single-chip mode] the bus cycle select bits (bits 4 and 5 at address 5f 16 ) is not used in the single-chip mode. however, do not make those bits state of not selected in all cases. especially in low-speed running, rewrite both bits at the same time to 01 2 , 10 2 or 11 2 . these bits are cleared to 00 2 at reset. b7 b6 b5 b4 b3 b2 b1 b0 processor mode register 1 (address 5f 16 ) bit 5 bus cycle select bits 3 2 1, 0 bit name at reset 0 rw functions in high-speed running 0 0 : 5 access in high-speed running 0 1 : 4 access in high-speed running 1 0 : 3 access in high-speed running 1 1 : not selected note: fix this bit to 0 when f(x in ) > 25 mhz. fix these bits to 0. 4 7, 6 rw rw rw rw 0 0 0 clock source for peripheral devices select bit (note) 0 : divided by 2 1 : cpu running speed select bit (note) 0 : high-speed running 1 : low-speed running rw 0 rw 0 b5 b4 in low-speed running 0 0 : not selected 0 1 : 4 access in low-speed running 1 0 : 3 access in low-speed running 1 1 : 2 access in low-speed running b5 b4 fix these bits to 0. 000 0 fig. 2.5.5 structure of processor mode register 1
chapter 3 input/output pins 3.1 programmable i/o ports 3.2 i/o pins of internal peripheral devices
input/output pins 3C2 7751 group users manual this chapter describes the programmable i/o ports in the single-chip mode. for p0 to p4, which change their functions according to the processor mode, refer also to the section 2.5 processor modes and chapter 12. connection with external devices. 3.1 programmable i/o ports the 7751 group has 68 programmable i/o ports, p0 to p8. the programmable i/o ports have direction registers and port registers in the sfr area. figure 3.1.1 shows the memory map of direction registers and port registers. p4 2 and p5 to p8 also function as the i/o pins of the internal peripheral devices. for the functions, refer to the section 3.2 i/o pins of internal peripheral devices and relevant sections of each internal peripheral devices. fig. 3.1.1 memory map of direction registers and port registers 3.1 programmable i/o ports port p4 register port p5 register port p4 direction register port p5 direction register port p6 register port p7 register port p6 direction register port p7 direction register port p8 register port p8 direction register 8 16 9 16 a 16 b 16 c 16 d 16 e 16 f 16 10 16 11 16 12 16 13 16 14 16 addresses port p0 register port p1 register port p0 direction register port p1 direction register port p2 register port p3 register port p2 direction register port p3 direction register 2 16 3 16 4 16 5 16 6 16 7 16
7751 group users manual 3C3 input/output pins 3.1.1 direction register this register determines the input/output direction of the programmable i/o port. each bit of this register corresponds one for one to each pin of the microcomputer. figure 3.1.2 shows the structure of port pi (i = 0 to 8) direction register. 3.1 programmable i/o ports bit bit name functions 0 1 2 3 4 5 6 7 port pi 0 direction bit port pi 2 direction bit port pi 3 direction bit port pi 4 direction bit port pi 6 direction bit 0 : input mode (functions as an input port) 1 : output mode (functions as an output port) port pi 5 direction bit port pi direction register (i = 0 to 8) (addresses 4 16 , 5 16 , 8 16 , 9 16 , c 16 , d 16 , 10 16 , 11 16 , 14 16 ) b1 b0 b2 b3 b4 b5 b6 b7 port pi 1 direction bit port pi 7 direction bit at reset rw 0 0 0 0 0 0 0 0 rw rw rw rw rw rw rw rw note: bits 7 to 4 of the port p3 direction register cannot be written and are fixed to 0 at reading. bit corresponding pin b7 b6 b5 b4 b3 b2 b1 b0 pi 7 pi 6 pi 5 pi 4 pi 3 pi 2 pi 1 pi 0 fig. 3.1.2 structure of port pi (i = 0 to 8) direction register
input/output pins 3C4 7751 group users manual 3.1.2 port register data is input/output to/from externals by writing/reading data to/from the port register. the port register consists of a port latch which holds the output data and a circuit which reads the pin state. each bit of the port register corresponds one for one to each pin of the microcomputer. figure 3.1.3 shows the structure of the port pi (i = 0 to 8) register. l when outputting data from programmable i/o ports set to output mode by writing data to the corresponding bit of the port register, the data is written into the port latch. the data is output from the pin according to the contents of the port latch. by reading the port register of a port set to output mode, the contents of the port latch is read out, instead of the pin state. accordingly, the output data is correctly read without being affected by an external load. (refer to figures 3.1.4 and 3.1.5.) l when inputting data from programmable i/o ports set to input mode the pin which is set to input mode enters the floating state. by reading the corresponding bit of the port register, the data which is input from the pin can be read out. by writing data to the port register of a programmable i/o port set to input mode, the data is only written into the port latch and is not output to externals. the pin retains floating. 3.1 programmable i/o ports
7751 group users manual 3C5 input/output pins 3.1 programmable i/o ports bit bit name functions 0 1 2 3 4 5 6 7 port pi 0 port pi 2 port pi 3 port pi 4 port pi 6 data is input/output to/from a pin by reading/writing from/to the corres- ponding bit. port pi 5 port pi register (i = 0 to 8) (addresses 2 16 , 3 16 , 6 16 , 7 16 , a 16 , b 16 , e 16 , f 16 , 12 16 ) b1 b0 b2 b3 b4 b5 b6 b7 port pi 1 port pi 7 at reset rw undefined note: bits 7 to 4 of the port p3 register cannot be written and are fixed to 0 at reading. undefined undefined undefined undefined undefined undefined undefined 0 : l level 1 : h level rw rw rw rw rw rw rw rw fig. 3.1.3 port pi (i = 0 to 8) register structure
input/output pins 3C6 7751 group users manual figures 3.1.4 and 3.1.5 show the port peripheral circuits. 3.1 programmable i/o ports fig. 3.1.4 port peripheral circuits (1) ports p0 0 to p0 7 , p1 0 to p1 7 , p2 0 to p2 7 , p3 0 to p3 3 , p4 3 to p4 6 [inside dotted-line not included] data bus direction register port latch ports p4 2 / 1 , p8 3 /txd 0 , p8 7 /txd 1 [inside dotted-line not included. ] ports p5 0 /ta0 out , p5 2 /ta1 out , p5 4 /ta2 out , p5 6 /ta3 out , p6 0 /ta4 out [inside dotted-line included. ] data bus 1 output port latch direction register p8 2 /rxd 0 , p8 6 /rxd 1 ports p4 0 , p4 1 , p4 7 , p5 1 /ta0 in , p5 3 /ta1 in , p5 5 /ta2 in , p5 7 /ta3 in , p6 1 /ta4 in , [inside dotted-line included] p6 2 /int 0 to p6 4 /int 2 , p6 5 /tb0 in to p6 7 /tb2 in , (there is no hysteresis for p8 2 /rxd 0 and p8 6 /rxd 1 .) ports p7 0 /an 0 to p7 6 /an 6 port p7 7 /an 7 /ad trg data bus analog input direction register port latch [ inside dotted-line not included] [ inside dotted-line included]
7751 group users manual 3C7 input/output pins 3.1 programmable i/o ports fig. 3.1.5 port peripheral circuits (2) e output pin ports p8 0 /cts 0 /rts 0 , p8 1 /clk 0 , p8 4 /cts 1 /rts 1 , p8 5 /clk 1 1 output 0 direction register port latch data bus
input/output pins 3C8 7751 group users manual 3.2 i/o pins of internal peripheral devices (p4 2 , p5Cp8) p4 2 and p5 to p8 also function as the i/o pins of the internal peripheral devices. table 3.2.1 lists i/o pins for the internal peripheral devices. for their functions, refer to relevant sections of each internal peripheral device. for the clock f 1 output pin, refer to chapter 12. connection with external devices. table 3.2.1 i/o pins for internal peripheral devices i/o pins for internal peripheral devices clock f 1 output pin i/o pins of timer a input pins of external interrupts input pins of timer b input pins of a-d converter i/o pins of serial i/o port p4 2 p5 p6 0 , p6 1 p6 2 to p6 4 p6 5 to p6 7 p7 p8 3.2 i/o pins of internal peripheral devices
chapter 4 interrupts 4.1 overview 4.2 interrupt sources 4.3 interrupt control 4.4 interrupt priority level 4.5 interrupt priority level detection circuit 4.6 interrupt priority level detection time 4.7 sequence from acceptance of interrupt request to execution of interrupt routine 4.8 return from interrupt routine 4.9 multiple interrupts ____ 4.10 external interrupts (int i interrupt) 4.11 precautions when using interrupts
7751 group users manual interrupts 4C2 the suspension of the current operation in order to perform another operation owing to a certain factor is referred to as interrupt. this chapter describes the interrupts. 4.1 overview the m37751 has 19 interrupt sources to generate interrupt requests. figure 4.1.1 shows the interrupt processing sequence. when an interrupt request is accepted, a branch is made to the start address of the interrupt routine set in the interrupt vector table (addresses ffd6 16 to ffff 16 ). set the start address of each interrupt routine at each interrupt vector address in the interrupt vector table. 4.1 overview fig. 4.1.1 interrupt processing sequence interrupt routine accept interrupt request resume processing suspend processing return to original routine rti instruction process interrupt executing routine branch to start address of interrupt routine
7751 group users manual 4C3 interrupts when an interrupt request is accepted, the contents of the registers listed below immediately preceding the acceptance of the interrupt request are automatically saved to the stack area in order of registers ? ? a . program bank register (pg) program counter (pc l , pc h ) a processor status register (ps l , ps h ) figure 4.1.2 shows the state of the stack area just before entering the interrupt routine. execute the rti instruction at the end of this interrupt routine to return to the routine that the microcomputer was executing before the interrupt request was accepted. as the rti instruction is executed, the register contents saved in the stack area are restored in order of registers a ? ? , and a return is made to the routine executed before the acceptance of interrupt request and processing is resumed from it. when an interrupt request is accepted and the rti instruction is executed, the only above registers to a are automatically saved and restored. when there are any other registers of which contents are necessary to be kept, use software to save and restore them. fig. 4.1.2 state of stack area just before entering interrupt routine 4.1 overview [s] is an initial value that the stack pointer (s) indicates at accepting an interrupt request. the ss contents become [s] C 5 after saving the above registers. address [s] C 4 [s] C 3 [s] C 2 [s] C 1 [s] ] processor status registers low-order byte (ps l ) stack area [s] C 5 processor status registers high-order byte (ps h ) program counters low-order byte (pc l ) program counters high-order byte (pc h ) program bank register (pg) ]
7751 group users manual interrupts 4C4 remarks non-maskable non-maskable software interrupt non-maskable software interrupt not used usually non-maskable interrupt ____ external interrupt due to int 0 pin input signal ____ external interrupt due to int 1 pin input signal ____ external interrupt due to int 2 pin input signal internal interrupt from timer a0 internal interrupt from timer a1 internal interrupt from timer a2 internal interrupt from timer a3 internal interrupt from timer a4 internal interrupt from timer b0 internal interrupt from timer b1 internal interrupt from timer b2 internal interrupt from uart0 internal interrupt from uart1 internal interrupt from a-d converter 4.2 interrupt sources table 4.2.1 lists the interrupt sources and the interrupt vector addresses. when programming, set the start address of each interrupt routine at the vector addresses listed in this table. 4.2 interrupt sources low-order address fffe 16 fffc 16 fffa 16 fff8 16 fff6 16 fff4 16 fff2 16 fff0 16 ffee 16 ffec 16 ffea 16 ffe8 16 ffe6 16 ffe4 16 ffe2 16 ffe0 16 ffde 16 ffdc 16 ffda 16 ffd8 16 ffd6 16 interrupt vector address table 4.2.1 interrupt sources and interrupt vector addresses high-order address ffff 16 fffd 16 fffb 16 fff9 16 fff7 16 fff5 16 fff3 16 fff1 16 ffef 16 ffed 16 ffeb 16 ffe9 16 ffe7 16 ffe5 16 ffe3 16 ffe1 16 ffdf 16 ffdd 16 ffdb 16 ffd9 16 ffd7 16 interrupt source reset zero division brk instruction ____ dbc (note) watchdog timer ____ int 0 ____ int 1 ____ int 2 timer a0 timer a1 timer a2 timer a3 timer a4 timer b0 timer b1 timer b2 uart0 receive uart0 transmit uart1 receive uart1 transmit a-d conversion ____ note: the dbc interrupt source is used exclusively for debugger control.
7751 group users manual 4C5 interrupts table 4.2.2 lists occurrence factors of internal interrupt request, which occur due to internal operation. 4.2 interrupt sources table 4.2.2 occurrence factors of internal interrupt request interrupt zero division interrupt brk instruction interrupt watchdog timer interrupt timer ai interrupt (i = 0 to 4) timer bi interrupt (i = 0 to 2) uarti receive interrupt (i = 0, 1) uarti transmit interrupt (i = 0, 1) a-d conversion interrupt interrupt request occurrence factors occurs when 0 is specified as the divisor for the div instruction (division instruction). (refer to 7751 series software manual. ) occurs when the brk instruction is executed. (refer to 7751 series software manual. ) occurs when the most significant bit of the watchdog timer becomes 0. (refer to chapter 9. watchdog timer. ) differs according to the timer ais operating modes. (refer to chapter 5. timer a. ) differs according to the timer bis operating modes. (refer to chapter 6. timer b. ) occurs at serial data reception. (refer to chapter 7. serial i/o. ) occurs at serial data transmission. (refer to chapter 7. serial i/o. ) occurs when a-d conversion is completed. (refer to chapter 8. a-d converter. )
7751 group users manual interrupts 4C6 4.3 interrupt control the enabling and disabling of maskable interrupts are controlled by the following : ?interrupt request bit ?interrupt priority level select bits ?processor interrupt priority level (ipl) ?interrupt disable flag (i) the interrupt disable flag (i) and the processor interrupt priority level (ipl) are assigned to the processor status register (ps). the interrupt request bit and the interrupt priority level select bits are assigned to the interrupt control register of each interrupt. figure 4.3.1 shows the memory assignment of the interrupt control registers, and figure 4.3.2 shows their structure. l maskable interrupt: an interrupt of which requests acceptance can be disabled by software. l non-maskable interrupt (including zero division, brk instruction, watchdog timer interrupts) : an interrupt which is certain to be accepted when its request occurs. these interrupts do not have their interrupt control registers and are independent of the interrupt disable flag (i). 4.3 interrupt control fig. 4.3.1 memory assignment of interrupt control registers a-d conversion interrupt control register uart0 transmit interrupt control register uart0 receive interrupt control register uart1 transmit interrupt control register uart1 receive interrupt control register timer a0 interrupt control register timer a1 interrupt control register timer a2 interrupt control register timer a3 interrupt control register timer a4 interrupt control register timer b0 interrupt control register timer b1 interrupt control register timer b2 interrupt control register int 0 interrupt control register int 1 interrupt control register int 2 interrupt control register address 70 16 71 16 72 16 73 16 74 16 75 16 76 16 77 16 78 16 79 16 7a 16 7b 16 7c 16 7d 16 7e 16 7f 16
7751 group users manual 4C7 interrupts 4.3 interrupt control fig. 4.3.2 structure of interrupt control register b7 b6 b5 b4 b3 b2 b1 b0 a-d conversion, uart0 and 1 transmit, uart0 and 1 receive, timers a0 to a4, timers b0 to b2 interrupt control registers (addresses 70 16 to 7c 16 ) bit 7 to 4 interrupt request bit 2 1 0 bit name at reset 0 rw functions 0 0 0 : level 0 (interrupt disabled) 0 0 1 : level 1 low level 0 1 0 : level 2 0 1 1 : level 3 1 0 0 : level 4 1 0 1 : level 5 1 1 0 : level 6 1 1 1 : level 7 high level b2 b1 b0 0 : no interrupt request 1 : interrupt request interrupt priority level select bits 3 rw rw rw rw C undefined 0 0 0 nothing is assigned. b7 b6 b5 b4 b3 b2 b1 b0 int 0 to int 2 interrupt control registers (addresses 7d 16 to 7f 16 ) bit 4 interrupt request bit (note) 2 1 0 bit name at reset 0 rw functions 0 0 0 : level 0 (interrupt disabled) 0 0 1 : level 1 low level 0 1 0 : level 2 0 1 1 : level 3 1 0 0 : level 4 1 0 1 : level 5 1 1 0 : level 6 1 1 1 : level 7 high level b2 b1 b0 0 : no interrupt request 1 : interrupt request 0 : edge sense 1 : level sense note: the int 0 to int 2 interrupt request bits are invalid when selecting the level sense. interrupt priority level select bits 3 7, 6 5 rw rw rw rw rw rw C 0 0 undefined 0 0 0 polarity select bit 0 : set the interrupt request bit at h level for level sense and at falling edge for edge sense. 1 : set the interrupt request bit at l level for level sense and at rising edge for edge sense. level sense/edge sense select bit nothing is assigned.
7751 group users manual interrupts 4C8 4.3.1 interrupt disable flag (i) all maskable interrupts can be disabled by this flag. when this flag is set to 1, all maskable interrupts are disabled; when the flag is cleared to 0, those interrupts are enabled. because this flag is set to 1 at reset, clear the flag to 0 when enabling interrupts. 4.3.2 interrupt request bit when an interrupt request occurs, this bit is set to 1. the bit remains set to 1 until the interrupt request is accepted, and it is cleared to 0 when the interrupt request is accepted. this bit also can be set to 0 or 1 by software. ____ ____ for the int i interrupt request bit (i = 0 to 2), when using the int i interrupt with level sense, the bit is ignored. 4.3.3 interrupt priority level select bits and processor interrupt priority level (ipl) the interrupt priority level select bits are used to determine the priority level of each interrupt. use the seb or clb instruction to set these bits. when an interrupt request occurs, its interrupt priority level is compared with the processor interrupt priority level (ipl). the requested interrupt is enabled only when the comparison result meets the following condition. accordingly, an interrupt can be disabled by setting its interrupt priority level to 0. each interrupt priority level > processor interrupt priority level (ipl) table 4.3.1 lists the setting of interrupt priority level, and table 4.3.2 lists the interrupt enabled level corresponding to ipl contents. all the interrupt disable flag (i), interrupt request bit, interrupt priority level select bits, and processor interrupt priority level (ipl) are independent of one another; they do not affect one another. interrupt requests are accepted only when the following conditions are satisfied. ?interrupt disable flag (i) = 0 ?interrupt request bit = 1 ?interrupt priority level > processor interrupt priority level (ipl) 4.3 interrupt control
7751 group users manual 4C9 interrupts b0 0 1 0 1 0 1 0 1 b2 0 0 0 0 1 1 1 1 table 4.3.1 setting of interrupt priority level b1 0 0 1 1 0 0 1 1 level 0 (interrupt disabled) level 1 level 2 level 3 level 4 level 5 level 6 level 7 low high 4.3 interrupt control interrupt priority level interrupt priority level select bits priority ipl 2 0 0 0 0 1 1 1 1 enabled interrupt priority level enable level 1 and above interrupts. enable level 2 and above interrupts. enable level 3 and above interrupts. enable level 4 and above interrupts. enable level 5 and above interrupts. enable level 6 and level 7 interrupts. enable only level 7 interrupt. disable all maskable interrupts. ipl 1 0 0 1 1 0 0 1 1 ipl 0 0 1 0 1 0 1 0 1 table 4.3.2 interrupt enabled level corresponding to ipl contents ipl 0 : bit 8 in processor status register (ps) ipl 1 : bit 9 in processor status register (ps) ipl 2 : bit 10 in processor status register (ps)
7751 group users manual interrupts 4C10 4.4 interrupt priority level when two or more interrupt requests are detected at the same sampling timing, at which whether an interrupt request exists or not is checked, in the case of the interrupt disable flag (i) = 0 (interrupts enabled); they are accepted in order of priority levels, with the highest priority interrupt request accepted first. among a total of 19 interrupt sources, the user can set the desired priority levels for 16 interrupt sources except software interrupts (zero division and brk instruction interrupts) and the watchdog timer interrupt. use the interrupt priority level select bits to set their priority levels. additionally, the reset, which is handled as one that has the highest priority of all interrupts, and the watchdog timer interrupt have their priority levels set by hardware. figure 4.4.1 shows the interrupt priority levels set by hardware. note that software interrupts are not affected by interrupt priority levels. whenever the instruction is executed, a branch is certain to be made to the interrupt routine. fig. 4.4.1 interrupt priority levels set by hardware 4.4 interrupt priority level watchdog timer reset 16 interrupt sources except software interrupts and watchdog timer interrupt the user can set the desired priority levels inside of the dotted line. priority levels determined by hardware high low priority level ??????????????????
7751 group users manual 4C11 interrupts 4.5 interrupt priority level detection circuit the interrupt priority level detection circuit selects the interrupt having the highest priority level when more than one interrupt request occurs at the same sampling timing. figure 4.5.1 shows the interrupt priority level detection circuit. 4.5 interrupt priority level detection circuit fig. 4.5.1 interrupt priority level detection circuit a-d conversion uart1 transmit uart1 receive uart0 transmit uart0 receive timer b2 timer b1 timer b0 timer a4 timer a3 timer a2 timer a1 timer a0 int 2 int 1 int 0 ipl processor interrupt priority level the highest priority level interrupt interrupt disable flag (i) watchdog timer interrupt reset accepting of interrupt request interrupt priority level interrupt priority level level 0 (initial value)
7751 group users manual interrupts 4C12 the following explains the operation of the interrupt priority detection circuit using figure 4.5.2. the interrupt priority level of a requested interrupt (y in figure 4.5.2) is compared with the resultant priority level sent from the preceding comparator (x in figure 4.5.2); whichever interrupt of the higher priority level is sent to the next comparator (z in figure 4.5.2). (initial comparison value is 0.) for interrupts for which no interrupt request occurs, the priority level sent from the preceding comparator is forwarded to the next comparator. when the two priority levels are found the same by comparison, the priority level sent from the preceding comparator is forwarded to the next comparator. accordingly, when the same priority level is set by software, the interrupt requests are subject to the following relation about priority: a-d conversion > uart1 transmit > uart1 receive > uart0 transmit > uart0 receive > timer b2 ____ ____ ____ > timer b1 > timer b0 > timer a4 > timer a3 > timer a2 > timer a1 > timer a0 > int 2 > int 1 > int 0 among the multiple interrupt requests sampled at the same time, one that has the highest priority level is detectedd by the above comparison. then this highest interrupt priority level is compared with the processor interrupt priority level (ipl). when this interrupt priority level is higher than the processor interrupt priority level (ipl) and the interrupt disable flag (i) is 0, the interrupt request is accepted. a interrupt request which is not accepted here is retained until it is accepted or its interrupt request bit is cleared to 0 by software. the interrupt priority is detected when the cpu fetches an op code, which is called the cpus op-code fetch cycle. however, when an op-code fetch cycle is generated during detection of an interrupt priority, new detection of that does not start. (refer to figure 4.6.1.) since the state of the interrupt request bit and interrupt priority levels are latched during detection of interrupt priority, even if the bit state and priority levels change, the detection is performed on the previous state before it has changed. 4.5 interrupt priority level detection circuit fig. 4.5.2 interrupt priority level detection model y x z comparator (priority level comparison) l when x y then z = x l when x y then z = y interrupt source y x : resultant priority level sent from the preceding comparator (highest priority at this point) y : priority level of interrupt source y z : highest priority at this point time <
7751 group users manual interrupts 4C13 4.6 interrupt priority level detection time after sampling had started, an interrupt priority level detection time has elapses before an interrupt request is accepted. the interrupt priority level detection time can be selected by software. figure 4.6.1 shows the interrupt priority level detection time. as the interrupt priority level detection time, normally select 2 cycles of internal clock f . 4.6 interrupt priority level detection time fig. 4.6.1 interrupt priority level detection time (2) interrupt priority level detection time op code fetch cycle sampling pulse (a) 7 cycles (b) 4 cycles (c) 2 cycles interrupt priority level detection time (note) note: pulse exists when 2 cycles of is selected. b7 b6 b5 b4 b3 b2 b1 b0 0 0 0 0 1 1 0 1 1 processor mode register 0 (address 5e 16 processor mode bits software reset bit fix to 0. clock 1 output select bit 7 cycles of [(a) shown below] 4 cycles of [(b) shown below] 2 cycles of [(c) shown below] interrupt priority detection time select bits not selected (1) interrupt priority detection time select bits b5, b4 fix to 0. 0 f f f
7751 group users manual interrupts 4C14 4.7 sequence from acceptance of interrupt request to execution of interrupt routine the sequence from the acceptance of interrupt request to the execution of the interrupt routine is described below. when an interrupt request is accepted, the interrupt request bit which corresponds to the accepted interrupt is cleared to 0, and then the interrupt processing starts from the next cycle of completion of the instruction which is being executed at accepting the interrupt request. figure 4.7.1 shows the sequence from acceptance of interrupt request to execution of interrupt routine. after execution of an instruction at accepting the interrupt request is completed, an intack (interrupt acknowledge) sequence is executed, and a branch is made to the start address of the interrupt routine allocated in addresses 0 16 to ffff 16 . the intack sequence is automatically performed in the following order. the contents of the program bank register (pg) just before performing the intack sequence are stored to stack. the contents of the program counter (pc) just before performing the intack sequence are stored to stack. a the contents of the processor status register (ps) just before performing the intack sequence is stored to stack. ? the interrupt disable flag (i) is set to 1. ? the interrupt priority level of the accepted interrupt is set into the processor interrupt priority level (ipl). ? the contents of the program bank register (pg) are cleared to 00 16 , and the contents of the interrupt vector address are set into the program counter (pc). performing the intack sequence requires at least 15 cycles of internal clock f . figure 4.7.2 shows the intack sequence timing. execution is started beginning with an instruction at the start address of the interrupt routine after completing the intack sequence. 4.7 sequence from acceptance of interrupt request to execution of interrupt routine
7751 group users manual interrupts 4C15 4.7 sequence from acceptance of interrupt request to execution of interrupt routine fig. 4.7.1 sequence from acceptance of interrupt request to execution of interrupt routine 00 00 00 00 00 00 data l(cpu) a h(cpu) a m a l(cpu) cpu pg e data h(cpu) 00 00 00 0000 0000 [s] [s]C2 [s]C4 [s]C4 0000 ffxx 16 ad m ` ad l ps h ipl ps l ad m ad l pc h pc l intack sequence [s] : contents of stack pointer (s) ffxx 16 : vector address l when 2 access in low-speed running and stack pointer(s)s content is even undefined undefined undefined undefined next instruction next instruction vector address (low order) fig. 4.7.2 intack sequence timing (at minimum) @ @ : duration for detecting interrupt priority level interrupt request occurs. interrupt request is accepted. instruction 1 instruction 2 intack sequence instructions in interrupt routine interrupt response time time @ time from the occurrence of an interrupt request until the completion of executing an instruction which is being executed at the occurrence. time from the instruction next to (note) until the completion of executing an instruction which is being done at the end of priority detection note : at this time, interrupt priority detection starts. a time required to execute the intack sequence (15 cycles of f at minimum) a f f
7751 group users manual interrupts 4C16 4.7.1 change in ipl at acceptance of interrupt request when an interrupt request is accepted, the processor interrupt priority level (ipl) is replaced with the interrupt priority level of the accepted interrupt. this results in easy control of multiple interrupts. (refer to section 4.9 multiple interrupts. ) when at reset or the watchdog timer or the software interrupt is accepted, the value shown in table 4.7.1 is set in the ipl. table 4.7.1 change in ipl at interrupt request acceptance change in ipl level 0 (000 2 ) is set. level 7 (111 2 ) is set. no change no change interrupt priority level of the accepted interrupt request is set. interrupt source reset watchdog timer zero division brk instruction other interrupts 4.7 sequence from acceptance of interrupt request to execution of interrupt routine
7751 group users manual interrupts 4C17 4.7.2 storing registers the register storing operation performed during intack sequence depends on whether the contents of the stack pointer (s) at accepting interrupt request are even or odd. when the contents of the stack pointer (s) are even, the contents of the program counter (pc) and the processor status register (ps) are stored as a 16-bit unit simultaneously at each other. when the contents of the stack pointer (s) are odd, they are stored with twice by an 8-bit unit for each. figure 4.7.3 shows the register storing operation. in the intack sequence, only the contents of the program bank register (pg), program counter (pc), and processor status register (ps) are stored to the stack area. the other necessary registers must be stored by software at the beginning of the interrupt routine. using the psh instruction can store all cpu registers except the stack pointer (s). 4.7 sequence from acceptance of interrupt request to execution of interrupt routine fig. 4.7.3 register storing operation storing is completed with 3 times. a stores 16 bits at a time. stores 16 bits at a time. (1) content of stack pointer (s) is even low-order byte of processor status register (ps l ) program bank register (pg) address [s] C 4 (even) [s] C 3 (odd) [s] C 2 (even) [s] C 1 (odd) [s] (even) storing order [s] C 5 (odd) address [s] C 4 (odd) [s] C 3 (even) [s] C 2 (odd) [s] C 1 (even) [s] (odd) a ? ? stores by each 8 bits. storing order storing is completed with 5 times. [s] C 5 (even) high-order byte of processor status register (ps h ) low-order byte of program counter (pc l ) high-order byte of program counter (pc h ) (2) content of stack pointer (s) is odd low-order byte of processor status register (ps l ) program bank register (pg) high-order byte of processor status register (ps h ) low-order byte of program counter (pc l ) high-order byte of program counter (pc h ) [s] is an initial value that the stack pointer (s) indicates at accepting an interrupt request. the ss contents become [s] C 5 after storing the above registers. ]
7751 group users manual interrupts 4C18 4.8 return from interrupt routine when the rti instruction is executed at the end of the interrupt routine, the contents of the program bank register (pg), program counter (pc), and processor status register (ps) immediately before performing the intack sequence, which were saved to the stack area, are automatically restored, and control returns to the routine executed before the acceptance of interrupt request and processing is resumed from it left off. for any register that is saved by software in the interrupt routine, restore it with the same data length and same register length as it was saved by using the pul instruction and others before executing the rti instruction. 4.9 multiple interrupts when a branch is made to the interrupt routine, the microcomputer becomes the following situation: ?interrupt disable flag (i) = 1 (interrupts disabled) ?interrupt request bit of the accepted interrupt = 0 ?processor interrupt priority level (ipl) = interrupt priority level of the accepted interrupt accordingly, as long as the ipl remains unchanged, the microcomputer can accept the interrupt request that has higher priority than the interrupt request being executed now by clearing the interrupt disable flag (i) to 0 in the interrupt routine. this is multiple interrupts. figure 4.9.1 shows the multiple interrupt mechanism. the interrupt requests that have not been accepted owing to their low priority levels are retained. when the rti instruction is executed, the interrupt priority level of the routine that the microcomputer was executing before accepting the interrupt request is restored to the ipl. therefore, one of the interrupt requests being retained is accepted when the following condition is satisfied at next detection of interrupt priority level: interrupt priority level of interrupt request being retained > processor interrupt priority level (ipl) 4.8 return from interrupt routine 4.9 multiple interrupts
7751 group users manual interrupts 4C19 4.9 multiple interrupts fig. 4.9.1 multiple interrupt mechanism main routine reset i = 1 ipl = 0 i = 0 interrupt 1 i = 1 ipl = 3 i = 0 i = 1 ipl = 5 rti i = 0 ipl = 3 rti i = 0 ipl = 0 i = 1 ipl = 2 rti i = 0 ipl = 0 interrupt 1 this request cannot be accepted because its priority level is lower than interrupt 1s. request time : they are set automatically. : set by software. i : interrupt disable flag ipl : processor interrupt priority level multiple interrupt interrupt 2 interrupt priority level=5 interrupt 3 interrupt priority level=2 interrupt 2 interrupt 3 interrupt 3 the instruction of main routine is not executed then. interrupt priority level=3 nesting
7751 group users manual interrupts 4C20 ___ 4.10 external interrupts (int i interrupt) ___ an external interrupt request occurs by input signals to the int i (i = 0 to 2) pin. the occurrence factor of interrupt request can be selected by the level sense/edge sense select bit and the polarity select bit (bits ___ 5 and 4 at addresses 7d 16 to 7f 16 ) shown in figure 4.10.1. table 4.10.1 lists the occurrence factor of int i interrupt request. ___ ___ when using p6 2 /int 0 to p6 4 /int 2 pins as input pins of external interrupts, set the corresponding bits at address 10 16 (port p6 direction register) to 0. (refer to figure 4.10.2.) ___ the signals input to the int i pin require h or l level width of 250 ns or more independent of the f(x in ). ___ ___ additionally, even when using the pins p6 2 /int 0 to p6 4 /int 2 as the input pins of external interrupt, the user can obtain the pins state by reading bits 2 to 4 at address e 16 (port p6 register). note: when selecting an input signals falling or l level as the occurrence factor of an interrupt request, make sure that the input signal is held l for 250 ns or more. when selecting an input signals rising or h level as that, make sure that the input signal is held h for 250 ns or more. ___ 4.10 external interrupts (int i interrupt) ___ table 4.10.1 occurrence factor of int i interrupt request b4 0 1 0 1 b5 0 0 1 1 ___ int i interrupt request occurrence factor ___ ___ the int i interrupt request occurs by always detecting the int i pins state. accordingly, when the user does ___ ___ not use the int i interrupt, set the int i interrupts priority level to level 0. ___ interrupt request occurs at falling of the signal input to the int i pin (edge sense). ___ interrupt request occurs at rising of the signal input to the int i pin (edge sense). ___ interrupt request occurs while the int i pin level is h (level sense). ___ interrupt request occurs while the int i pin level is l (level sense).
7751 group users manual interrupts 4C21 ___ 4.10 external interrupts (int i interrupt) ___ fig. 4.10.1 structure of int i (i=0 to 2) interrupt control register b7 b6 b5 b4 b3 b2 b1 b0 int 0 to int 2 interrupt control registers (addresses 7d 16 to 7f 16 ) bit 4 interrupt request bit (note) 2 1 0 bit name at reset 0 rw functions 0 0 0 : level 0 (interrupt disabled) 0 0 1 : level 1 low level 0 1 0 : level 2 0 1 1 : level 3 1 0 0 : level 4 1 0 1 : level 5 1 1 0 : level 6 1 1 1 : level 7 high level b2 b1 b0 0 : no interrupt request 1 : interrupt request 0 : edge sense 1 : level sense note: the int 0 to int 2 interrupt request bits are invalid when selecting the level sense. interrupt priority level select bits 3 7, 6 5 rw rw rw rw rw rw C 0 0 undefined 0 0 0 polarity select bit 0 : set the interrupt request bit at h level for level sense and at falling edge for edge sense. 1 : set the interrupt request bit at l level for level sense and at rising edge for edge sense. level sense/edge sense select bit nothing is assigned.
7751 group users manual interrupts 4C22 ___ 4.10 external interrupts (int i interrupt) bit corresponding pin functions 0 1 2 3 4 5 6 7 ta4 out pin int 0 pin int 1 pin int 2 pin tb1 in pin tb0 in pin port p6 direction register (address 10 16 ) b1 b0 b2 b3 b4 b5 b6 b7 ta4 in pin tb2 in pin at reset rw 0 0 0 0 0 0 0 0 rw rw rw rw rw rw rw rw 0 : input mode 1 : output mode when using pins as external interrupt input pins,set the corresponding bits to 0. : bits 0, 1 and bits 5 to 7 are not used for external interrupts. fig. 4.10.2 relationship between port p6 direction register and input pins of external interrupt
7751 group users manual interrupts 4C23 ___ 4.10.1 function of int i interrupt request bit (1) selecting edge sense mode the interrupt request bit has the same function as that of internal interrupts. that is, when an interrupt request occurs, the interrupt request bit is set to 1. the bit remains set to 1 until the interrupt request is accepted; it is cleared to 0 when the interrupt request is accepted. by software, this bit also can be set to 0 in order to clear the interrupt request or 1 in order to generate the interrupt request. (2) selecting level sense mode ___ the int i interrupt request bit becomes ignored. ___ in this case, the interrupt request occurs continuously while the level of the int i pin is valid level ] 1 . ___ ___ when the int i pin level changes from the valid level to the invalid level ] 2 before the int i interrupt request is accepted, this interrupt request is not retained. (refer to figure 4.10.4.) valid level ] 1 : this means the level which is selected by the polarity select bit (bit 4 at addresses 7d 16 to 7f 16 ). invalid level ] 2 : this means the reversed level of a valid level. ___ 4.10 external interrupts (int i interrupt) int i pin edge detection circuit interrupt request level sense/edge sense select bit data bus interrupt request bit 0 1 ___ fig. 4.10.3 circuit of int i interrupt
7751 group users manual interrupts 4C24 ___ fig. 4.10.4 occurrence of int i interrupt request in level sense mode ___ 4.10 external interrupts (int i interrupt) first interrupt routine int i pin level valid invalid main routine interrupt request is accepted. return to main routine. second interrupt routine third interrupt routine main routine when the int i pins level changes to an invalid level before an interrupt request is accepted, the interrupt request is not retained.
7751 group users manual interrupts 4C25 ___ 4.10 external interrupts (int i interrupt) ___ 4.10.2 switch of occurrence factor of int i interrupt request ___ to switch the occurrence factor of int i interrupt request from the level sense to the edge sense, set the ___ int i interrupt control register in the sequence shown in figure 4.10.5 (1). to change the polarity, set the ___ int i interrupt control register in the sequence shown in figure 4.10.5 (2). ___ fig. 4.10.5 switching flow of occurrence factor of int i interrupt request clear level sense/edge sense select bit to 0 ( select edge sense ) clear interrupt request bit to 0 set the interrupt priority level to level 0 ( disable int i interrupt ) set polarity select bit clear interrupt request bit to 0 (2) changing polarity (1) switching from level sense to edge sense set the interrupt priority level to level 1C7 (enable acceptance of int i interrupt request) set the interrupt priority level to level 1C7 (enable acceptance of int i interrupt request) set the interrupt priority level to level 0 ( disable int i interrupt ) note: follow the above procedure each. do not perform 2 or more setting at the same time, with 1 instruction.
7751 group users manual interrupts 4C26 4.11 precautions when using interrupts 4.11 precautions when using interrupts to change the interrupt priority level select bits (bits 0 to 2 at addresses 70 16 to 7f 16 ), 2 to 7 cycles of f are required after executing an write-instruction until completion of the interrupt priority levels change. accordingly, it is necessary to reserve enough time by software when changing the interrupt priority level of which interrupt source is the same within a very short execution time consisting of a few instructions. figure 4.11.1 shows a program example to reserve time required for changing interrupt priority level. the time for change depends on the interrupt priority detection timer select bits (bits 4 and 5 at address 5e 16 ). table 4.11.1 lists the relation between the number of instructions to be inserted with program example of figure 4.11.1 and the interrupt priority detection time select bits. fig. 4.11.1 program example to reserve time required for changing interrupt priority level table 4.11.1 relation between number of instructions to be inserted with program example of figure 4.11.1 and interrupt priority detection time select bits interrupt priority detection time select bits (note) interrupt priority level detection time 7 cycles of f 4 cycles of f 2 cycles of f do not select. number of inserted instructions nop instruction 4 or more nop instruction 2 or more nop instruction 1 or more b5 0 0 1 1 b4 0 1 0 1 note: we recommend [b5 = 1, b4 = 0]. ; write to interrupt priority level select bits ; insert nop instruction (note) ; ; ; write to interrupt priority level select bits note: all instructions (other than instructions for writing to address 7x 16 ) which have the same cycles as nop instruction can also be inserted. confirm the number of instructions to be inserted by table 4.11.1. : ldm.b #0xh, 007xh nop nop nop ldm.b #0xh, 007xh :
chapter 5 timer a 5.1 overview 5.2 block description 5.3 timer mode 5.4 event counter mode 5.5 one-shot pulse mode 5.6 pulse width modulation (pwm) mode
7751 group users manual timer a 5.1 overview 5C2 timer a is used primarily for output to externals. it consists of five counters, timers a0 to a4, each equipped with a 16-bit reload function. timers a0 to a4 operate independently of one another. 5.1 overview timer ai (i = 0 to 4) has four operating modes listed below. except for the event counter mode, timers a0 to a4 all have the same functions. l timer mode the timer counts an internally generated count source. following functions can be used in this mode: ?gate function ?pulse output function l event counter mode the timer counts an external signal. following functions can be used in this mode: ?pulse output function ?two-phase pulse signal processing function (timers a2, a3, and a4) l one-shot pulse mode the timer outputs a pulse which has an arbitrary width once. l pulse width modulation (pwm) mode timer outputs pulses which have an arbitrary width in succession. the timer functions as which pulse width modulator as follows: ?16-bit pulse width modulator ?8-bit pulse width modulator
timer a 7751 group users manual 5C3 5.2 block description 5.2 block description figure 5.2.1 shows the block diagram of timer a. explanation of relevant registers to timer a is described below. fig. 5.2.1 block diagram of timer a data bus (odd) data bus (even) f 2 /f 4 f 16 /f 32 f 64 /f 128 f 512 /f 1024 count source select bits timer mode one-shot pulse mode pwm mode polarity switching timer mode (gate function) event counter mode trigger count start bit down-count up-down bit (low-order 8 bits) (high-order 8 bits) timer ai reload register (16) timer ai counter (16) timer ai interrupt request bit up-count/down-count switching (always down-count except for event counter mode) toggle f.f. pulse output function select bit tai in tai out
timer a 7751 group users manual 5C4 5.2 block description 5.2.1 counter and reload register (timer ai register) each of timer ai counter and reload register consists of 16 bits. the counter down-counts each time the count source is input. in the event counter mode, it can also function as an up-counter. the reload register is used to store the initial value of the counter. when the counter underflows or overflows, the reload registers contents are reloaded into the counter. values are set to the counter and reload register by writing a value to the timer ai register. table 5.2.1 lists the memory assignment of the timer ai register. the value written into the timer ai register when counting is not in progress is set to the counter and reload register. the value written into the timer ai register when counting is in progress is set to only the reload register. in this case, the reload registers updated contents are transferred to the counter at the next reload time. the value got when reading out the timer ai register varies according to the operating mode. table 5.2.2 lists reading and writing from and to the timer ai register. table 5.2.2 reading and writing from and to timer ai register write written to only reload register. written to both counter and reload register. operating mode timer mode event counter mode one-shot pulse mode pulse width modulation (pwm) mode note: when reset, the contents of the timer ai register are undefined. notes 1: also refer to [precautions when operating in timer mode] and [precautions when oper- ating in event counter mode]. 2: when reading and writing to/from the timer ai register, perform them in a unit of 16 bits. read counter value is read out. ( note 1 ) undefined value is read out. table 5.2.1 memory assignment of timer ai register timer ai register high-order byte low-order byte timer a0 register address 47 16 address 46 16 timer a1 register address 49 16 address 48 16 timer a2 register address 4b 16 address 4a 16 timer a3 register address 4d 16 address 4c 16 timer a4 register address 4f 16 address 4e 16
timer a 7751 group users manual 5C5 5.2 block description 5.2.2 count start register this register is used to start and stop counting. each bit of this register corresponds to each timer. figure 5.2.2 shows the structure of the count start register. fig. 5.2.2 structure of count start register bit timer b2 count start bit timer b1 count start bit timer b0 count start bit timer a4 count start bit timer a3 count start bit timer a2 count start bit timer a1 count start bit timer a0 count start bit bit name at reset 0 0 0 0 0 0 0 0 rw functions b7 b6 b5 b4 b3 b2 b1 b0 count start register (address 40 16 ) 0 : stop counting 1 : start counting rw rw rw rw rw rw rw rw 0 1 2 3 4 5 6 7 : bits 7 to 5 are not used for timer a.
timer a 7751 group users manual 5C6 5.2 block description 5.2.3 timer ai mode register figure 5.2.3 shows the structure of the timer ai mode register. operating mode select bits are used to select the operating mode of timer ai. bits 2 to 7 have different functions according to the operating mode. these bits are described in the paragraph of each operating mode. fig. 5.2.3 structure of timer ai mode register bit 7 5 4 3 1 bit name at reset 0 0 0 0 0 0 0 0 rw functions b7 b6 b5 b4 b3 b2 b1 b0 timer ai mode register (i = 0 to 4) (addresses 56 16 to 5a 16 ) 0 0 : timer mode 0 1 : event counter mode 1 0 : one-shot pulse mode 1 1 : pulse width modulation (pwm) mode b1 b0 these bits have different functions according to the operating mode. operating mode select bits 6 2 0 rw rw rw rw rw rw rw rw
timer a 7751 group users manual 5C7 5.2 block description 5.2.4 timer ai interrupt control register figure 5.2.4 shows the structure of the timer ai interrupt control register. for details about interrupts, refer to chapter 4. interrupts. fig. 5.2.4 structure of timer ai interrupt control register (1) interrupt priority level select bits (bits 2 to 0) these bits select a timer ai interrupts priority level. when using timer ai interrupts, select priority levels 1 to 7. when a timer ai interrupt request occurs, its priority level is compared with the processor interrupt priority level (ipl), so that the requested interrupt is enabled only when its priority level is higher than the ipl. (however, this applies when the interrupt disable flag (i) = 0.) to disable timer ai interrupts, set these bits to 000 2 (level 0). (2) interrupt request bit (bit 3) this bit is set to 1 when the timer ai interrupt request occurs. this bit is automatically cleared to 0 when the timer ai interrupt request is accepted. this bit can be set to 1 or 0 by software. b7 b6 b5 b4 b3 b2 b1 b0 bit 7 to 4 interrupt request bit 2 1 0 bit name at reset 0 rw functions 0 0 0 : level 0 (interrupt disabled) 0 0 1 : level 1 low level 0 1 0 : level 2 0 1 1 : level 3 1 0 0 : level 4 1 0 1 : level 5 1 1 0 : level 6 1 1 1 : level 7 high level b2 b1 b0 0 : no interrupt request 1 : interrupt request interrupt priority level select bits 3 rw rw rw rw C undefined 0 0 0 nothing is assigned. timer ai interrupt control registers (i = 0 to 4) (addresses 75 16 to 79 16 )
timer a 7751 group users manual 5C8 5.2 block description 5.2.5 port p5 and port p6 direction registers the i/o pins of timers a0 to a3 are shared with port p5, and the i/o pins of timer a4 are shared with port p6. when using these pins as timer ais input pins, set the corresponding bits of the port p5 and port p6 direction registers to 0 to set these ports for the input mode. when used as timer ais output pins, these pins are forcibly set to output pins of timer ai regardless of the direction registerss contents. figure 5.2.5 shows the relationship between the port p5 and port p6 direction registers and the timer ais i/o pins. fig. 5.2.5 relationship between port p5 and port p6 direction registers and timer ais i/o pins bit corresponding pin name functions 0 1 2 3 4 5 6 7 ta0 out pin ta1 out pin ta1 in pin ta2 out pin ta3 out pin 0: input mode 1: output mode when using these pins as timer ais input pins, set the corresponding bits to 0. ta2 in pin port p5 direction register (address d 16 ) b1 b0 b2 b3 b4 b5 b6 b7 ta0 in pin ta3 in pin at reset rw 0 0 0 0 0 0 0 0 0 1 2 3 4 5 6 7 ta4 out pin int 0 pin int 1 pin int 2 pin tb1 in pin tb0 in pin port p6 direction register (address 10 16 ) b1 b0 b2 b3 b4 b5 b6 b7 ta4 in pin tb2 in pin rw 0 0 0 0 0 0 0 0 : bits 7 to 2 are not used for timer a. corresponding pin name functions bit at reset 0: input mode 1: output mode when using these pins as timer ais input pins, set the corresponding bits to 0. rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw
timer a 7751 group users manual 5C9 5.3 timer mode 5.3 timer mode in this mode, the timer counts an internally generated count source. (refer to table 5.3.1.) figure 5.3.1 shows the structures of the timer ai mode register and timer ai register in the timer mode. table 5.3.1 specifications of timer mode item count source count operation count start condition count stop condition interrupt request occurrence timing tai in pin function tai out pin function read from timer ai register write to timer ai register specifications f 2 /f 4 , f 16 /f 32 , f 64 /f 128 , or f 512 /f 1024 ? down-count ? when the counter underflows, reload registers contents are reloaded and counting continues. when count start bit is set to 1. when count start bit is cleared to 0. when the counter underflows. programmable i/o port or gate input programmable i/o port or pulse output counter value can be read out. l while counting is stopped when a value is written to timer ai register, it is written to both reload register and counter. l while counting is in progress when a value is written to timer ai register, it is written to only reload register. (transferred to counter at next reload timing.)
timer a 7751 group users manual 5C10 5.3 timer mode fig. 5.3.1 structures of timer ai mode register and timer ai register in timer mode b7 b0 b7 b0 (b15) (b8) timer a0 register (addresses 47 16 , 46 16 ) timer a1 register (addresses 49 16 , 48 16 ) timer a2 register (addresses 4b 16 , 4a 16 ) timer a3 register (addresses 4d 16 , 4c 16 ) timer a4 register (addresses 4f 16 , 4e 16 ) functions bit at reset rw 15 to 0 these bits can be set to 0000 16 to ffff 16 . assuming that the set value = n, the counter divides the count source frequency by n + 1. when reading, the register indicates the counter value. undefined rw gate function select bits pulse output function select bit 1 operating mode select bits bit name functions b7 b6 b5 b4 b3 b2 b1 b0 timer ai mode register (i = 0 to 4) (addresses 56 16 to 5a 16 ) 0 0 : timer mode 0 : no pulse output (tai out pin functions as a programmable i/o port.) 1 : pulse output (tai out pin functions as a pulse output pin.) 0 0 : f 2 /f 4 0 1 : f 16 /f 32 1 0 : f 64 /f 128 1 1 : f 512 /f 1024 b7 b6 count source select bits b1 b0 b4 b3 0 0 0 0 : no gate function 0 1 : (tai in pin functions as a prog- rammable i/o port.) 1 0 : gate function (counter counts only while tai in pins input signal is l level.) 1 1 : gate function (counter counts only while tai in pins input signal is h level.) bit 4 at reset rw 0 2 0rw 0rw 0 rw 3 0rw 0 rw 5 0 rw 6 7 0rw 0 rw fix this bit to 0 in the timer mode. 0
timer a 7751 group users manual 5C11 5.3 timer mode 5.3.1 setting for timer mode figures 5.3.2 and 5.3.3 show an initial setting example for registers relevant to the timer mode. note that when using interrupts, set up to enable the interrupts. for details, refer to section chapter 4. interrupts. fig. 5.3.2 initial setting example for registers relevant to timer mode (1) note : counter divides the count source frequency by n + 1. setting divide ratio b7 b0 can be set to 0000 16 to ffff 16 (n). (b15) (b8) b7 b0 timer a0 register (addresses 47 16 , 46 16 ) timer a1 register (addresses 49 16 , 48 16 ) timer a2 register (addresses 4b 16 , 4a 16 ) timer a3 register (addresses 4d 16 , 4c 16 ) timer a4 register (addresses 4f 16 , 4e 16 ) continue to figure 5.3.3 on next page. b7 b0 pulse output function select bit 0: no pulse output. 1: pulses output. 00 selecting timer mode and each function timer ai mode register (i = 0 to 4) (addresses 56 16 to 5a 16 ) count source select bits 0 0: f 2 /f 4 0 1: f 16 /f 32 1 0: f 64 /f 128 1 1: f 512 /f 1024 b7 b6 gate function select bits 0 0: 0 1: 1 0: gate function (counter counts only while tai in pins input signal is l level.) 1 1: gate function (counter counts only while tai in pins input signal is h level.) b4 b3 selection of timer mode no gate function 0
timer a 7751 group users manual 5C12 5.3 timer mode fig. 5.3.3 initial setting example for registers relevant to timer mode (2) count starts setting count start bit to 1. b7 b0 count start register (address 40 16 ) timer a0 count start bit timer a1 count start bit timer a2 count start bit timer a3 count start bit timer a4 count start bit setting interrupt priority level b7 b0 timer ai interrupt control register (i = 0 to 4) (addresses 75 16 to 79 16 ) interrupt priority level select bits when using interrupts, set these bits to level 1C7. when disabling interrupts, set these bits to level 0. from preceding figure 5.3.2 . setting port p5 and port p6 direction registers b7 b0 port p5 direction register (address d 16 ) ta0 in pin ta1 in pin ta2 in pin b7 b0 port p6 direction register (address 10 16 ) when gate function is selected, set the bit corresponding to the tai in pin to 0. ta4 in pin ta3 in pin
timer a 7751 group users manual 5C13 5.3 timer mode 5.3.2 count source in the timer mode, the count source select bits (bits 6 and 7 at addresses 56 16 to 5a 16 ) select the count source. table 5.3.2 lists the count source frequency. table 5.3.2 count source frequency f(x in ) = 25 mhz clock source for peripheral devices select bit = 0 count source f 4 f 32 f 128 f 1024 f(x in ) = 40 mhz b6 0 1 0 1 count source select bits b7 0 0 1 1 frequency 6.25 mhz 781.25 khz 195.3125 khz 24.4141 khz clock source for peripheral devices select bit = 1 clock source for peripheral devices select bit = 0 count source f 4 f 32 f 128 f 1024 count source f 2 f 16 f 64 f 512 frequency 12.5 mhz 1.5625 mhz 390.625 khz 48.8281 khz frequency 10 mhz 1.25 mhz 312.5 khz 39.0625 khz clock source for peripheral devices select bit : bit 2 at address 5f 16
timer a 7751 group users manual 5C14 5.3 timer mode 5.3.3 operation in timer mode when the count start bit is set to 1, the counter starts counting of the count source. when the counter underflows, the reload registers contents are reloaded and counting continues. a the timer ai interrupt request bit is set to 1 when the counter underflows in . the interrupt request bit remains set to 1 until the interrupt request is accepted or the interrupt request bit is cleared to 0 by software. figure 5.3.4 shows an example of operation in the timer mode. fig. 5.3.4 example of operation in timer mode (without pulse output and gate functions) stops counting. restarts counting. ffff 16 n 0000 16 time count start bit timer ai interrupt request bit 1 1 counter contents (hex.) n = reload registers contents cleared to 0 when interrupt request is accepted or cleared by software. set to 1 by software. starts counting. 0 0 1 / f i 5 (n+1) fi = frequency of count source (f 2 /f 4 , f 16 /f 32 , f 64 /f 128 , f 512 /f 1024 ) cleared to 0 by software. set to 1 by software.
timer a 7751 group users manual 5C15 5.3 timer mode 5.3.4 select function the following describes the selective gate and pulse output functions. (1) gate function the gate function is selected by setting the gate function select bits (bits 4 and 3 at addresses 56 16 to 5a 16 ) to 10 2 or 11 2 . the gate function makes it possible to start or stop counting depending on the tai in pins input signal. table 5.3.3 lists the count valid levels. figure 5.3.5 shows an example of operation selecting the gate function. when selecting the gate function, set the port p5 and port p6 direction registers bits which correspond to the tai in pin for the input mode. additionally, make sure that the tai in pins input signal has a pulse width equal to or more than two cycles of the count source. table 5.3.3 count valid levels gate function select bits count valid level (duration when counter counts) b4 b3 1 0 while tai in pins input signal is l level 1 1 while tai in pins input signal is h level note: the counter does not count while the tai in pins input signal is not at the count valid level.
timer a 7751 group users manual 5C16 5.3 timer mode ffff 16 n 0000 16 time 1 1 0 0 starts counting. n = reload registers contents counter contents (hex.) stops counting. set to 1 by software. count start bit tai in pins input signal count valid level timer ai interrupt request bit cleared to 0 when interrupt request is accepted or cleared by software. the counter counts when the count start bit = 1 and the tai in pins input signal is at the count valid level. the counter stops counting while the tai in pins input signal is not at the count valid level, and the counter value is retained. invalid level fig. 5.3.5 example of operation selecting gate function
timer a 7751 group users manual 5C17 5.3 timer mode (2) pulse output function the pulse output function is selected by setting the pulse output function select bit (bit 2 at addresses 56 16 to 5a 16 ) to 1. when this function is selected, the tai out pin is forcibly set for the pulse output pin regardless of the corresponding bits of the port p5 and port p6 direction registers. the tai out pin outputs pulses of which polarity is inverted each time the counter underflows. when the count start bit (address 40 16 ) is 0 (count stopped), the tai out pin outputs l level. figure 5.3.6 shows an example of operation selecting the pulse output function. fig. 5.3.6 example of operation selecting pulse output function ffff 16 n 0000 16 time count start bit timer ai interrupt request bit 1 1 counter contents (hex.) n = reload registers contents cleared to 0 when interrupt request is accepted or cleared by software. set to 1 by software. starts counting. pulse output from taiout pin h 0 l 0 set to 1 by software. cleared to 0 by software. starts counting. restarts counting.
timer a 7751 group users manual 5C18 5.3 timer mode [precautions when operating in timer mode] by reading the timer ai register, the counter value can be read out at any timing while counting is in progress. however, if the timer ai register is read at the reload timing shown in figure 5.3.7, the value ffff 16 is read out. when reading the timer ai register after setting a value to the register while counting is not in progress and before the counter starts counting, the set value is read out correctly. fig. 5.3.7 reading timer ai register 210 n n C 1 counter value (hex.) 21 0 ffff n C 1 read value (hex.) reload time n = reload registers contents
timer a 7751 group users manual 5C19 5.4 event counter mode 5.4 event counter mode in this mode, the timer counts an external signal. (refer to tables 5.4.1 and 5.4.2.) figure 5.4.1 shows the structures of the timer ai mode register and timer ai register in the event counter mode. table 5.4.1 specifications of event counter mode (when not using two-phase pulse signal processing function) item count source count operation count start condition count stop condition interrupt request occurrence timing tai in pin function tai out pin function read from timer ai register write to timer ai register specifications l external signal input to the tai in pin l the count sources valid edge can be selected between the falling and the rising edges by software. l up-count or down-count can be switched by external signal or software. l when the counter overflows or underflows, reload registers contents are reloaded and counting continues. when count start bit is set to 1. when count start bit is cleared to 0. when the counter overflows or underflows. count source input programmable i/o port, pulse output, or up-count/down-count switch signal input counter value can be read out. l while counting is stopped when a value is written to timer ai register, it is written to both reload register and counter. l while counting is in progress when a value is written to timer ai register, it is written to only reload register. (transferred to counter at next reload time.)
timer a 7751 group users manual 5C20 5.4 event counter mode item count source count operation count start condition count stop condition interrupt request occurrence timing taj in , taj out (j = 2 to 4) pin function read from timer aj register write to timer aj register table 5.4.2 specifications of event counter mode (when using two-phase pulse signal processing function with timers a2, a3, and a4) specifications external signal (two-phase pulse) input to the taj in or taj out pin (j = 2 to 4) l up-count or down-count can be switched by external signal (two- phase pulse). l when the counter overflows or underflows, reload registers contents are reloaded and counting is continued. when count start bit is set to 1. when count start bit is cleared to 0. when the counter overflows or underflows. two-phase pulse input counter value can be read out. l while counting is stopped when a value is written to timer a2, a3, or a4 register, it is written to both reload register and counter. l while counting is in progress when a value is written to timer a2, a3, or a4 register, it is written to only reload register. (transferred to counter at next reload time.)
timer a 7751 group users manual 5C21 5.4 event counter mode fig. 5.4.1 structures of timer ai mode register and timer ai register in event counter mode b7 b6 b5 b4 b3 b2 b1 b0 001 bit up-down switching factor select bit count polarity select bit bit name these bits are ignored in event counter mode. fix this bit to 0 in event counter mode. 5 : it may be either 0 or 1. 7 functions 0 : counts at falling edge of external signal 1 : counts at rising edge of external signal 0 : contents of up-down register 1 : input signal to tai out pin at reset 0 0 0 0 0 rw pulse output function select bit operating mode select bits 1 0 : no pulse output (tai out pin functions as a programmable i/o port.) 1 : pulse output (tai out pin functions as a pulse output pin.) 0 1 : event counter mode b1 b0 0 0 0 55 0 2 rw rw 3 4 5 6 rw rw rw rw rw rw timer ai mode register (i = 0 to 4) (addresses 56 16 to 5a 16 ) b7 b0 b7 b0 (b15) (b8) timer a0 register (addresses 47 16 , 46 16 ) timer a1 register (addresses 49 16 , 48 16 ) timer a2 register (addresses 4b 16 , 4a 16 ) timer a3 register (addresses 4d 16 , 4c 16 ) timer a4 register (addresses 4f 16 , 4e 16 ) rw 15 to 0 bit functions at reset rw these bits can be set to 0000 16 to ffff 16 . assuming that the set value = n, the counter divides the count source frequency by n + 1 when down-counting, or by ffff 16 C n + 1 when up-counting. when reading, the register indicates the counter value. undefined
timer a 7751 group users manual 5C22 5.4 event counter mode 5.4.1 setting for event counter mode figures 5.4.2 and 5.4.3 show an initial setting example for registers relevant to the event counter mode. note that when using interrupts, set up to enable the interrupts. for details, refer to chapter 4. interrupts. fig. 5.4.2 initial setting example for registers relevant to event counter mode (1) [ the counter divides the count source frequency by n + 1 when down-counting, or by ffff 16 C n + 1 when up- counting. continue to figure 5.4.3 on next page. b7 b0 01 0 selecting event counter mode and each function timer ai mode register (i = 0 to 4) (addresses 56 16 to 5a 16 ) pulse output function select bit 0: no pulse output 1: pulse output count polarity select bit 0: counts at falling edge of external signal. 1: counts at rising edge of external signal. up-down switching factor select bit 0: contents of up-down register 1: input signal to tai out pin 5 : it may be either 0 or 1. selection of event counter mode setting divide ratio b7 b0 can be set to 0000 16 to ffff 16 (n). (b15) (b8) b7 b0 timer a0 register (addresses 47 16 , 46 16 ) timer a1 register (addresses 49 16 , 48 16 ) timer a2 register (addresses 4b 16 , 4a 16 ) timer a3 register (addresses 4d 16 , 4c 16 ) timer a4 register (addresses 4f 16 , 4e 16 ) 55 b7 b0 setting upCdown register upCdown register (address 44 16 ) timer a0 upCdown bit timer a1 upCdown bit timer a2 upCdown bit timer a3 upCdown bit timer a4 upCdown bit timer a2 twoCphase pulse signal processing select bit timer a3 twoCphase pulse signal processing select bit timer a4 twoCphase pulse signal processing select bit set the corresponding upCdown bit when the contents of the up down register are selected as the up down switching factor. set the corresponding bit to 1 when the twoCphase pulse signal processing function is selected for timers a2 to a4. 0: downCcount 1: upCcount 0: twoCphase pulse signal processing function disabled 1: twoCphase pulse signal processing function enabled C C
timer a 7751 group users manual 5C23 5.4 event counter mode fig. 5.4.3 initial setting example for registers relevant to event counter mode (2) setting the count start bit to 1 b7 b0 count start register (address 40 16 ) timer a0 count start bit timer a1 count start bit timer a2 count start bit timer a3 count start bit timer a4 count start bit count starts from preceding figure 5.4.2 . setting port p5 and port p6 direction registers b7 b0 port p5 direction register (address d 16 ) ta0 in pin ta1 out pin ta1 in pin ta2 out pin ta2 in pin ta3 out pin b7 b0 port p6 direction register (address 10 16 ) clear the bit corresponding to the tai in pin to 0. when selecting the tai out pins input signal as up-down switching factor, set the bit corresponding to the tai out pin to 0. when selecting the twoCphase pulse signal processing function, set the bit corresponding to the taj out (j = 2 to 4) pin to 0. ta4 out pin ta4 in pin ta3 in pin ta0 out pin setting interrupt priority level b7 b0 timer ai interrupt control register (i = 0 to 4) (addresses 75 16 to 79 16 ) interrupt priority level select bits when using interrupts, set these bits to level 1-7. when disabling interrupts, set these bits to level 0.
timer a 7751 group users manual 5C24 5.4 event counter mode timer ai interrupt request bit ffff 16 n 0000 16 time count start bit 1 1 counter contents (hex.) n = reload registers contents cleared to 0 when interrupt request is accepted or cleared by software. set to 1 by software. starts counting. up-down bit 1 note: the above applies when the up-down bits contents are selected as the up-down switching factor (i.e., up-down switching factor select bit = 0 ). 0 0 0 set to 1 by software. 5.4.2 operation in event counter mode when the count start bit is set to 1, the counter starts counting of the count source. the counter counts the count sources valid edges. a when the counter underflows or overflows, the reload registers contents are reloaded and counting continues. ? the timer ai interrupt request bit is set to 1 when the counter underflows or overflows in a . the interrupt request bit remains set to 1 until the interrupt request is accepted or the interrupt request bit is cleared to 0 by software. figure 5.4.4 shows an example of operation in the event counter mode. fig. 5.4.4 example of operation in event counter mode (without pulse output function and two-phase pulse signal processing function)
timer a 7751 group users manual 5C25 5.4 event counter mode (1) switching between up-count and down-count the up-down register (address 44 16 ) or the input signal from the tai out pin is used to switch the up- count from and to the down-count. this switching is performed by the up-down bit when the up-down switching factor select bit (bit 4 at addresses 56 16 to 5a 16 ) is 0, and by the input signal from the tai out pin when the up-down switching factor select bit is 1. when switching the up-count/down-count, this switching is actually performed when the count sources next valid edge is input. l switching by up-down bit the counter down-counts when the up-down bit is 0, and up-counts when the up-down bit is 1. figure 5.4.5 shows the structure of the up-down register. l switching by tai out pins input signal the counter down-counts when the tai out pins input signal is at l level, and up-counts when the tai out pins input signal is at h level. when using the tai out pin input signal to switch the up-count/down-count, set the port p5 and p6 direction registers bits which correspond to the tai out pin for the input mode. fig. 5.4.5 structure of up-down register bit bit name at reset 0 0 0 0 0 rw functions b7 b6 b5 b4 b3 b2 b1 b0 up-down register (address 44 16 ) 0 0 0 timer a4 up-down bit timer a3 up-down bit timer a2 up-down bit timer a1 up-down bit timer a0 up-down bit timer a2 two-phase pulse signal processing select bit (note) timer a3 two-phase pulse signal processing select bit (note) timer a4 two-phase pulse signal processing select bit (note) 0 : down-count 1 : up-count this function is valid when the contents of the up-down register are selected as the up-down switching factor. 0 : disabled two-phase pulse signal processing function 1 : enabled two-phase pulse signal processing function when not using the two-phase pulse signal processing function, make sure to set the bit to 0. the value is 0 at reading. note: use the ldm or sta instruction when writing to bits 5 to 7. 0 1 2 3 4 5 6 7 rw rw rw rw rw wo wo wo
timer a 7751 group users manual 5C26 5.4 event counter mode 5.4.3 select functions the following describes the selective pulse output, and two-phase pulse signal processing functions. (1) pulse output function the pulse output function is selected by setting the pulse output function select bit (bit 2 at addresses 56 16 to 5a 16 ) to 1. when this function is selected, the tai out pin is forcibly set for the pulse output pin regardless of the corresponding bits of the port p5 and port p6 direction registers. the tai out pin outputs pulses of which polarity is inverted each time the counter underflows or overflows. (refer to figure 5.3.6.) when the count start bit (address 40 16 ) is 0 (count stopped), the tai out pin outputs l level.
timer a 7751 group users manual 5C27 5.4 event counter mode (2) two-phase pulse signal processing function (timers a2 to a4) for timers a2 to a4, the two-phase pulse signal processing function is selected by setting the two- phase pulse signal processing select bits (bits 5 to 7 at address 44 16 ) to 1. (refer to figure 5.4.5. ) figure 5.4.6 shows the timer a2, a3, and a4 mode registers when the two-phase pulse signal processing function is selected. with timers selecting the two-phase pulse signal processing function, the timer counts two kinds of pulses of which phases differ by 90 degrees. there are two types of the two-phase pulse signal processing: normal processing and quadruple processing. in timers a2 and a3, normal processing is performed; in timer a4, quadruple processing is performed. for some bits of the port p5 and p6 direction registers correspond to pins used for two-phase pulse input, set these bits for the input mode. l normal processing the timer up-counts the rising edges to the tak in pin when the phase has the relationship that the tak in pins input signal level goes from l to h while the tak out (k = 2 and 3) pins input signal is h level. the timer down-counts the falling edges to the tak in pin when the phase has the relationship that the tak in pins input signal level goes from h to l while the tak out pins input signal is h level. (refer to figure 5.4.7.) fig. 5.4.6 timer a2, a3, and a4 mode registers when two-phase pulse signal processing function is selected 1 00001 timer a2 mode register (address 58 16 ) timer a3 mode register (address 59 16 ) timer a4 mode register (address 5a 16 ) b7 b6 b5 b4 b3 b2 b1 b0 5 : it may be either 0 or 1. 55 fig. 5.4.7 normal processing tak out tak in (k=2, 3) h h l up count +1 +1 +1 C1 C1 C1 down- count l up- count up- count up- count down- count down- count
timer a 7751 group users manual 5C28 5.4 event counter mode l quadruple processing the timer up-counts all rising and falling edges to the ta4 out and ta4 in pins when the phase has the relationship that the ta4 in pins input signal level goes from l to h while the ta4 out pins input signal is h level. the timer down-counts all rising and falling edges to the ta4 out and ta4 in pins when the phase has the relationship that the ta4 in pins input signal level goes from h to l while the ta4 out pins input signal is h level. (refer to figure 5.4.8.) table 5.4.3 lists the input signals to the ta4 out and ta4 in pins when the quadruple processing is selected. table 5.4.3 ta4 out and ta4 in pins input signals when quadruple operation is selected input signal to ta4 out pin input signal to ta4 in pin h level l level rising falling h level l level rising falling rising falling l level h level falling rising h level l level up-count down-count fig. 5.4.8 quadruple processing ta4 out ta4 in h h l l +1 +1 +1 +1 +1 +1 +1 +1 +1 +1 up-count all edges C1 C1 C1 C1 C1 C1 C1 C1 C1 C1 down-count all edges up-count all edges down-count all edges
timer a 7751 group users manual 5C29 5.4 event counter mode [precautions when operating in event counter mode] 1. by reading the timer ai register, the counter value can be read out at any timing while counting is in progress. however, when the timer ai register is read at the reload timing shown in figure 5.4.9, a value ffff 16 (at the underflow) or 0000 16 (at the overflow) is read out. when reading the timer ai register after setting a value to the register while counting is not in progress and before the counter starts counting, the set value is read out correctly. fig. 5.4.9 reading timer ai register 2. the tai out pin is used for all functions listed below. accordingly, only one of these functions can be selected for each timer. ?switching between up-count and down-count by tai out pins input signal ?pulse output function ?two-phase pulse signal processing function for timers a2 to a4 210 n n C 1 counter value (hex.) 210 ffff n C 1 read value (hex.) reload time n = reload registers contents (1) for down-count fffd fffe ffff n n + 1 fffd fffe ffff 0000 n + 1 (2) for up-count counter value (hex.) read value (hex.) reload time n = reload registers contents
timer a 7751 group users manual 5C30 5.5 one-shot pulse mode 5.5 one-shot pulse mode in this mode, the timer outputs a pulse which has an arbitrary width once. (refer to table 5.5.1.) when a trigger occurs, the timer outputs h level from the tai out pin for an arbitrary time. figure 5.5.1 shows the structures of the timer ai mode register and timer ai register in the one-shot pulse mode. table 5.5.1 specifications of one-shot pulse mode item count source count operation count start condition count stop condition interrupt request occurrence timing tai in pin function tai out pin function read from timer ai register write to timer ai register specifications f 2 /f 4 , f 16 /f 32 , f 64 /f 128 , or f 512 /f 1024 l down-count l when the counter value becomes 0000 16 , reload registers con- tents are reloaded and counting stops. l if a trigger occurs during counting, reload registers contents are reloaded then and counting continues. l when a trigger occurs. ( note ) l internal or external trigger can be selected by software. l when the counter value becomes 0000 16 , l when count start bit is cleared to 0 when counting stops. programmable i/o port or trigger input one-shot pulse output an undefined value is read out. l while counting is stopped when a value is written to timer ai register, it is written to both reload register and counter. l while counting is in progress when a value is written to timer ai register, it is written to only reload register. (transferred to counter at next reload time.) note: the trigger is generated with the count start bit = 1.
timer a 7751 group users manual 5C31 5.5 one-shot pulse mode fig. 5.5.1 structures of timer ai mode register and timer ai register in one-shot pulse mode b7 b0 b7 b0 (b15) (b8) timer a0 register (addresses 47 16 , 46 16 ) timer a1 register (addresses 49 16 , 48 16 ) timer a2 register (addresses 4b 16 , 4a 16 ) timer a3 register (addresses 4d 16 , 4c 16 ) timer a4 register (addresses 4f 16 , 4e 16 ) rw 15 to 0 these bits can be set to 0000 16 to ffff 16 . assuming that the set value = n, the h level width of the one-shot pulse output from the tai out pin is expressed as follows : n / f i . undefined f i : frequency of count source (f 2 /f 4 , f 16 /f 32 , f 64 /f 128 , or f 512 /f 024 ) wo trigger select bits fix this bit to 1 in one-shot pulse mode. 1 @ bit name functions b7 b6 b5 b4 b3 b2 b1 b0 timer ai mode register (i = 0 to 4) (addresses 56 16 to 5a 16 ) 1 0 : one-shot pulse mode 7 0 0 : f 2 /f 4 0 1 : f 16 /f 32 1 0 : f 64 /f 128 1 1 : f 512 /f 1024 b7 b6 count source select bits b1 b0 b4 b3 fix this bit to 0 in one-shot pulse mode. 10 1 0 0 : writing 1 to one-shot start bit 0 1 : (tai in pin functions as a progra- mmable i/o port.) 1 0 : falling edge of tai in pins input signal 1 1 : rising edge of tai in pins input signal bit at reset 0 0 0 0 0 0 0 0 rw 0 4 0 2 3 5 6 rw rw rw rw rw rw rw rw operating mode select bits at reset bit functions
timer a 7751 group users manual 5C32 5.5 one-shot pulse mode 5.5.1 setting for one-shot pulse mode figures 5.5.2 and 5.5.3 show an initial setting example for registers relevant to the one-shot pulse mode. note that when using interrupts, set up to enable the interrupts. for details, refer to chapter 4. interrupts. fig. 5.5.2 initial setting example for registers relevant to one-shot pulse mode (1) continue to figure 5.5.3 . setting interrupt priority level b7 b0 timer ai interrupt control register (i = 0 to 4) (addresses 75 16 to 79 16 ) interrupt priority level select bits when using interrupts, set these bits to level 1-7. when disabling interrupts, set these bits to level 0. b7 b0 10 0 selecting one-shot pulse mode and each function timer ai mode register (i = 0 to 4) (addresses 56 16 to 5a 16 ) 1 trigger select bits 0 0 : 0 1 : 1 0 : falling of tai in pins input signal: external trigger 1 1 : rising of tai in pins input signal: external trigger b4 b3 count source select bits 0 0 : f 2 /f 4 0 1 : f 16 /f 32 1 0 : f 64 /f 128 1 1 : f 512 /f 1024 b7 b6 selection of one-shot pulse mode setting h level width of one-shot pulse b7 b0 can be set to 0000 16 to ffff 16 (n). (b15) (b8) b7 b0 timer a0 register (addresses 47 16 , 46 16 ) timer a1 register (addresses 49 16 , 48 16 ) timer a2 register (addresses 4b 16 , 4a 16 ) timer a3 register (addresses 4d 16 , 4c 16 ) timer a4 register (addresses 4f 16 , 4e 16 ) h level width = writing 1 to one-shot start bit: internal trigger fi note . n however, if n = 0000 16 , the counter does not operate and the tai out pin outputs l level. at this time, no timer ai interrupt request occurs. fi: frequency of count source
timer a 7751 group users manual 5C33 5.5 one-shot pulse mode fig. 5.5.3 initial setting example for registers relevant to one-shot pulse mode (2) trigger generated trigger input to tai in pin when internal trigger is selected when external trigger is selected from preceding figure 5.5.2 . b7 b0 one-shot start register (address 42 16 ) setting one-shot start bit to 1 timer a0 one-shot start bit timer a1 one-shot start bit timer a2 one-shot start bit timer a3 one-shot start bit timer a4 one-shot start bit setting count start bit to 1 b7 b0 timer a0 count start bit timer a1 count start bit timer a2 count start bit timer a3 count start bit timer a4 count start bit count start register (address 40 16 ) b7 b0 port p5 direction register (address d 16 ) setting port p5 and port p6 direction registers ta0 in pin ta1 in pin ta2 in pin ta3 in pin port p6 direction register (address 10 16 ) ta4 in pin b7 b0 set the corresponding bit to 0. setting count start bit to 1 b7 b0 timer a0 count start bit timer a1 count start bit timer a2 count start bit timer a3 count start bit timer a4 count start bit count start register (address 40 16 ) count starts
timer a 7751 group users manual 5C34 5.5 one-shot pulse mode 5.5.2 count source in the one-shot pulse mode, the count source select bits (bits 6 and 7 at addresses 56 16 to 5a 16 ) select the count source. table 5.5.2 lists the count source frequency. table 5.5.2 count source frequency f(x in ) = 25 mhz clock source for peripheral devices select bit = 0 count source f 4 f 32 f 128 f 1024 f(x in ) = 40 mhz b6 0 1 0 1 count source select bits b7 0 0 1 1 frequency 6.25 mhz 781.25 khz 195.3125 khz 24.4141 khz clock source for peripheral devices select bit = 1 clock source for peripheral devices select bit = 0 count source f 4 f 32 f 128 f 1024 count source f 2 f 16 f 64 f 512 frequency 12.5 mhz 1.5625 mhz 390.625 khz 48.8281 khz frequency 10 mhz 1.25 mhz 312.5 khz 39.0625 khz clock source for peripheral devices select bit : bit 2 at address 5f 16
timer a 7751 group users manual 5C35 5.5 one-shot pulse mode 5.5.3 trigger the counter is enabled for counting when the count start bit (address 40 16 ) is set to 1. the counter starts counting when a trigger is generated after it has been enabled. an internal or an external trigger can be selected as that trigger. an internal trigger is selected when the trigger select bits (bits 4 and 3 at addresses 56 16 to 5a 16 ) are 00 2 or 01 2 ; an external trigger is selected when the bits are 10 2 or 11 2 . if a trigger is generated during counting, the reload registers contents are reloaded and the counter continues counting. if generating a trigger during counting, make sure that a certain time which is equivalent to one cycle of the timers count source or more has passed between the previous generated trigger and a new generated trigger. (1) when selecting internal trigger a trigger is generated when writing 1 to the one-shot start bit (address 42 16 ). figure 5.5.4 shows the structure of the one-shot start register. (2) when selecting external trigger a trigger is generated at the falling of the tai in pins input signal when bit 3 at addresses 56 16 to 5a 16 is 0, or at its rising when bit 3 is 1. when using an external trigger, set the port p5 and p6 direction registers bits which correspond to the tai in pins for the input mode. fig. 5.5.4 structure of one-shot start register . bit 7 to 5 nothing is assigned. timer a4 one-shot start bit timer a3 one-shot start bit timer a2 one-shot start bit timer a1 one-shot start bit timer a0 one-shot start bit bit name at reset 0 0 undefined 0 0 0 rw functions b7 b6 b5 b4 b3 b2 b1 b0 one-shot start register (address 42 16 ) 1 : start outputting one-shot pulse (valid when selecting internal trigger.) the value is 0 at reading. 0 1 2 3 4 wo wo wo wo wo C
timer a 7751 group users manual 5C36 5.5 one-shot pulse mode 5.5.4 operation in one-shot pulse mode when the one-shot pulse mode is selected with the operating mode select bits, the tai out pin outputs l level. when the count start bit is set to 1, the counter is enabled for counting. after that, counting starts when a trigger is generated. a when the counter starts counting, the tai out pin outputs h level. (however, if the timer ai register has a value 0000 16 set in it, the counter does not operate and the output from the tai out pin remains l. the timer ai interrupt request does not occur.) ? when the counter value becomes 0000 16 , the output from the tai out pin becomes l level. additionally, the reload registers contents are reloaded and the counter stops counting there. ? simultaneously at ? , the timer ai interrupt request bit is set to 1. this interrupt request bit remains set to 1 until the interrupt request is accepted or the interrupt request bit is cleared to 0 by software. figure 5.5.5 shows an example of operation in the one-shot pulse mode. when a trigger is generated after ? above, the counter and tai out pin perform the same operations beginning from again. furthermore, if a trigger is generated during counting, the counter down-counts once after this generated new trigger, and it continues counting with the reload registers contents reloaded. if generating a trigger during counting, make sure that a certain time which is equivalent to one cycle of the timers count source or more has passed between the previous generated trigger and a new generated trigger. the one-shot pulse output from the tai out pin can be disabled by clearing the timer ai mode registers bit 2 to 0. accordingly, timer ai can be also used as an internal one-shot timer that does not perform the pulse output. in this case, the tai out pin functions as a programmable i/o port.
timer a 7751 group users manual 5C37 5.5 one-shot pulse mode fig. 5.5.5 example of operation in one-shot pulse mode (selecting external trigger) stops counting. starts counting. ffff 16 n 0001 16 time count start bit timer ai interrupt request bit 1 1 counter contents (hex.) n = reload registers contents cleared to 0 when interrupt request is accepted or cleared by software. set to 1 by software. starts counting. tai in pin input signal h one-shot pulse output from tai out pin h trigger during counting 1 / f i 5 (n) note: the above applies when an external trigger (rising of tai in pins input signal) is selected. 0 l l 0 1 / f i 5 (n+1) when the count start bit = 0 (counting stopped), the tai out pin outputs l level. when a trigger is generated during counting, the counter counts the count source n + 1 times after a new trigger is generated. fi = frequency of count source (f 2 /f 4 , f 16 /f 32 , f 64 /f 128 , or f 512 /f 1024 ) stops counting. reloaded reloaded
timer a 7751 group users manual 5C38 5.5 one-shot pulse mode [precautions when operating in one-shot pulse mode] 1. if the count start bit is cleared to 0 during counting, the counter stops counting and the tai out pins output level becomes l. at the same time, the timer ai interrupt request bit is set to 1. 2. a one-shot pulse is output synchronously with an internally generated count source. accordingly, when selecting an external trigger, there will be a delay equivalent to one cycle of count source at maximum from when a trigger is input to the tai in pin till when a one-shot pulse is output. note: the above applies when an external trigger (falling of tai in pins input signal) is selected. tai in pins input signal h l count source trigger input starts outputting of one-shot pulse one-shot pulse output from tai out pin output delay fig. 5.5.6 output delay in one-shot pulse output 3. when setting the timers operating mode in one of the followings, the timer ai interrupt request bit is set to 1. l when the one-shot pulse mode is selected after a reset l when the operating mode is switched from the timer mode to the one-shot pulse mode l when the operating mode is switched from the event counter mode to the one-shot pulse mode therefore, when using the timer ai interrupt (interrupt request bit), be sure to clear the timer ai interrupt request bit to 0 after above setting.
timer a 7751 group users manual 5C39 5.6 pulse width modulation (pwm) mode 5.6 pulse width modulation (pwm) mode in this mode, the timer continuously outputs pulses which have an arbitrary width. (refer to table 5.6.1.) figure 5.6.1 shows the structures of the timer ai mode register and timer ai register in the pwm mode. table 5.6.1 specifications of pwm mode item count source count operation count start condition count stop condition interrupt request occurrence timing tai in pin function tai out pin function read from timer ai register write to timer ai register specifications f 2 /f 4 , f 16 /f 32 , f 64 /f 128 , or f 512 /f 1024 l down-count (operating as an 8-bit or 16-bit pulse width modulator) l reload registers contents are reloaded at rising of pwm pulse and counting continues. l a trigger generated during counting does not affect the counting. l when a trigger is generated. l internal or external trigger can be selected by software. when count start bit is cleared to 0. at falling of pwm pulse programmable i/o port or trigger input pwm pulse output an undefined value is read out. l while counting is stopped when a value is written to timer ai register, it is written to both reload register and counter. l while counting is in progress when a value is written to timer ai register, it is written to only reload register. (transferred to counter at next reload time.)
timer a 7751 group users manual 5C40 5.6 pulse width modulation (pwm) mode fig. 5.6.1 structures of timer ai mode registers and timer ai registers in pwm mode b7 b0 b7 b0 timer a0 register (addresses 47 16 , 46 16 ) timer a1 register (addresses 49 16 , 48 16 ) timer a2 register (addresses 4b 16 , 4a 16 ) timer a3 register (addresses 4d 16 , 4c 16 ) timer a4 register (addresses 4f 16 , 4e 16 ) functions bit at reset rw 15 to 0 these bits can be set to 0000 16 to fffe 16 . assuming that the set value = n, the h level width of the pwm pulse output from the tai out pin is expressed as follows: undefined (b15) (b8) wo n f i f i : frequency of count source (f 2 /f 4 , f 16 /f 32 , f 64 /f 128 , or f 512 /f 1024 ) (b15) b7 b0 b7 b0 (b8) timer a0 register (addresses 47 16 , 46 16 ) timer a1 register (addresses 49 16 , 48 16 ) timer a2 register (addresses 4b 16 , 4a 16 ) timer a3 register (addresses 4d 16 , 4c 16 ) timer a4 register (addresses 4f 16 , 4e 16 ) functions bit at reset rw 7 to 0 15 to 8 undefined undefined these bits can be set to 00 16 to ff 16 . assuming that the set value = m, pwm pulses period output from the tai out pin is expressed as follows: (m + 1)(2 8 C 1) f i wo these bits can be set to 00 16 to fe 16 . assuming that the set value = n, the h level width of the pwm pulse output from the tai out pin is expressed as follows: n(m + 1) f i wo f i : frequency of count source (f 2 /f 4 , f 16 /f 32 , f 64 /f 128 , or f 512 /f 1024 ) b7 b6 b5 b4 b3 b2 b1 b0 timer ai mode register (i = 0 to 4) (addresses 56 16 to 5a 16 ) 7 0 0 : f 2 /f 4 0 1 : f 16 /f 32 1 0 : f 64 /f 128 1 1 : f 512 /f 1024 b7 b6 count source select bits 11 1 at reset 0 rw trigger select bits fix this bit to 1 in pwm mode. 1 operating mode select bits bit name functions 1 1 : pwm mode b1 b0 b4 b3 16/8-bit pwm mode select bit 0 0 : writing 1 to count start bit 0 1 : (tai in pin functions as a pro- grammable i/o port.) 1 0 : falling edge of tai in pins input signal 1 1 : rising edge of tai in pins input signal bit 0 : as a 16-bit pulse width modulator 1 : as an 8-bit pulse width modulator 4 0 2 3 5 6 0 0 0 0 0 0 0 rw rw rw rw rw rw rw rw
timer a 7751 group users manual 5C41 5.6 pulse width modulation (pwm) mode note: when operating as 8-bit pulse width modulator (m+1) (2 8 C 1) fi n(m+1) fi fi : frequency of count source however, if n = 00 16 , the pulse width modulator does not operate and the tai out pin outputs l level. at this time, no timer ai request occurs. b7 b0 count source select bits 0 0 : f 2 /f 4 0 1 : f 16 /f 32 1 0 : f 64 /f 128 1 1 : f 512 /f 1024 11 selecting pwm mode and each function timer ai mode register (i = 0 to 4) (addresses 56 16 to 5a 16 ) b7 b6 1 16/8-bit pwm mode select bit 0 : operates as 16-bit pulse width modulator 1 : operates as 8-bit pulse width modulator continue to figure 5.6.3 . trigger select bits 0 0 : 0 1 : 1 0 : falling of tai in pins input signal 1 1 : rising of tai in pins input signal b3 b4 selection of pwm mode setting pwm pulses period and h level width b7 b0 can be set to 0000 16 to fffe 16 (n) (b15) (b8) b7 b0 timer a0 register (addresses 47 16 , 46 16 ) timer a1 register (addresses 49 16 , 48 16 ) timer a2 register (addresses 4b 16 , 4a 16 ) timer a3 register (addresses 4d 16 , 4c 16 ) timer a4 register (addresses 4f 16 , 4e 16 ) note: when operating as 16-bit pulse width modulator (2 16 C 1) fi n fi fi : frequency of count source however, if n = 0000 16 , the pulse width modulator does not operate and the tai out pin outputs l level. at this time, no timer ai request occurs. l when operating as 16-bit pulse width modulator b7 b0 can be set to 00 16 to ff 16 (m) (b15) (b8) b7 b0 l when operating as 8-bit pulse width modulator can be set to 00 16 to fe 16 (n) timer a0 register (addresses 47 16 , 46 16 ) timer a1 register (addresses 49 16 , 48 16 ) timer a2 register (addresses 4b 16 , 4a 16 ) timer a3 register (addresses 4d 16 , 4c 16 ) timer a4 register (addresses 4f 16 , 4e 16 ) writing 1 to count start bit: internal trigger : external trigger : external trigger period = h level width = period = h level width = 5.6.1 setting for pwm mode figures 5.6.2 and 5.6.3 show an initial setting example for registers relevant to the pwm mode. note that when using interrupts, set up to enable the interrupts. for details, refer to chapter 4. interrupts. fig. 5.6.2 initial setting example for registers relevant to pwm mode (1)
timer a 7751 group users manual 5C42 5.6 pulse width modulation (pwm) mode count starts trigger input to tai in pin when external trigger is selected when internal trigger is selected from preceding figure5.6.2. trigger generated b7 b0 port p5 direction register (address d 16 ) setting port p5 and port p6 direction registers ta0 in pin ta1 in pin ta2 in pin ta3 in pin ta4 in pin b7 b0 clear the corresponding bit to 0. port p6 direction register (address 10 16 ) setting interrupt priority level b7 b0 timer ai interrupt control register (i = 0 to 4) (addresses 75 16 to 79 16 ) interrupt priority level select bits when using interrupts, set these bits to level 1 C 7. when disabling interrupts, set these bits to level 0. setting count start bit to 1 b7 b0 count start register (address 40 16 ) timer a1 count start bit timer a2 count start bit timer a3 count start bit timer a4 count start bit timer a0 count start bit setting count start bit to 1 b7 b0 count start register (address 40 16 ) timer a1 count start bit timer a2 count start bit timer a3 count start bit timer a4 count start bit timer a0 count start bit fig. 5.6.3 initial setting example for registers relevant to pwm mode (2)
timer a 7751 group users manual 5C43 5.6 pulse width modulation (pwm) mode 5.6.2 count source in the pwm mode, the count source select bits (bits 6 and 7 at addresses 56 16 to 5a 16 ) select the count source. table 5.6.2 lists the count source frequency. table 5.6.2 count source frequency f(x in ) = 25 mhz clock source for peripheral devices select bit = 0 count source f 4 f 32 f 128 f 1024 f(x in ) = 40 mhz b6 0 1 0 1 count source select bits b7 0 0 1 1 frequency 6.25 mhz 781.25 khz 195.3125 khz 24.4141 khz clock source for peripheral devices select bit = 1 clock source for peripheral devices select bit = 0 count source f 4 f 32 f 128 f 1024 count source f 2 f 16 f 64 f 512 frequency 12.5 mhz 1.5625 mhz 390.625 khz 48.8281 khz frequency 10 mhz 1.25 mhz 312.5 khz 39.0625 khz clock source for peripheral devices select bit : bit 2 at address 5f 16 5.6.3 trigger when a trigger is generated, the tai out pin starts outputting pwm pulses. an internal or an external trigger can be selected as that trigger. an internal trigger is selected when the trigger select bits (bits 4 and 3 at addresses 56 16 to 5a 16 ) are 00 2 or 01 2 ; an external trigger is selected when the bits are 10 2 or 11 2 . a trigger generated during outputting of pwm pulses is ignored and it does not affect the pulse output operation. (1) when selecting internal trigger a trigger is generated when writing 1 to the count start bit (at address 40 16 ). (2) when selecting external trigger a trigger is generated at the falling of the tai in pins input signal when bit 3 at addresses 56 16 to 5a 16 is 0, or at its rising when bit 3 is 1. however, the trigger input is accepted only when the count start bit is 1. when using an external trigger, set the port p5 and p6 direction registers bits which correspond to the tai in pins for the input mode.
timer a 7751 group users manual 5C44 5.6 pulse width modulation (pwm) mode 5.6.4 operation in pwm mode when the pwm mode is selected with the operating mode select bits, the tai out pin outputs l level. when a trigger is generated, the counter (pulse width modulator) starts counting and the tai out pin outputs a pwm pulse ( notes 1 and 2 ). a the timer ai interrupt request bit is set to 1 each time the pwm pulse level goes from h to l. the interrupt request bit remains set to 1 until the interrupt request is accepted or the interrupt request bit is cleared to 0 by software. ? each time a pwm pulse has been output for one period, the reload registers contents are reloaded and the counter continues counting. the following explains operation of the pulse width modulator. [16-bit pulse width modulator] when the 16/8-bit pwm mode select bit is set to 0, the counter operates as a 16-bit pulse width modulator. figures 5.6.4 and 5.6.5 show operation examples of the 16-bit pulse width modulator. [8-bit pulse width modulator] when the 16/8-bit pwm mode select bit is set to 1, the counter is divided into 8-bit halves. then, the high-order 8 bits operate as an 8-bit pulse width modulator, and the low-order 8 bits operate as an 8-bit prescaler. figures 5.6.6 and 5.6.7 show operation examples of the 8-bit pulse width modulator. notes 1: if a value 0000 16 is set into the timer ai register when the counter operates as a 16-bit pulse width modulator, the pulse width modulator does not operate and the output from the tai out pin remains l level. the timer ai interrupt request does not occur. similarly, if a value 00 16 is set into the high-order 8 bits of the timer ai register when the counter operates as an 8- bit pulse width modulator, the same is performed. 2: when the counter operates as an 8-bit pulse width modulator, the tai out pin outputs l level of the pwm pulse which has the same width as set h level of the pwm pulse after a trigger generated. after that, the pwm pulse output starts from the tai out pin.
timer a 7751 group users manual 5C45 5.6 pulse width modulation (pwm) mode fig. 5.6.4 operation example of 16-bit pulse width modulator fig. 5.6.5 operation example of 16-bit pulse width modulator (when counter value is updated during pulse output) 1 / f i 5 (2 16 C 1) 1 / f i 5 (n) count source tai in pins input signal pwm pulse output from tai out pin note: the above applies when reload register (n) = 0003 16 and an external trigger (rising of tai in pins input signal) is selected. trigger is not generated by this signal. h h l l timer ai interrupt request bit 1 0 cleared to 0 when interrupt request is accepted or cleared by software. fi: frequency of count source (f 2 /f 4 , f 16 /f 32 , f 64 /f 128 , or f 512 /f 1024 ) when an arbitrary value is set to the timer ai register after setting 0000 16 to it, the timing at which the pwm pulse goes h depends on the timing at which the new value is set. note: the above applies when an external trigger (rising of tai in pins input signal) is selected. fffe 16 n 0001 16 tai in pins input signal h counter contents (hex.) l h l (1 / f i ) 5 (2 16 C1) (2 16 C1) C n (1 / f i ) 5 (2 16 C1) pwm pulse output from tai out pin 0000 16 is set to timer ai register. 2000 16 is set to timer ai register. 2000 16 fffe 16 is set to timer ai register. n = reload registers contents fi: frequency of count source (f 2 /f 4 , f 16 /f 32 , f 64 /f 128 , or f 512 /f 1024 ) restarts counting. stops counting. time (1 / pf i ) 5 (2 C1) 16
timer a 7751 group users manual 5C46 5.6 pulse width modulation (pwm) mode fig. 5.6.6 operation example of 8-bit pulse width modulator count source tai in pins input signal 1 / f i 5 (m+1) 5 (2 8 C1) pwm pulse output from tai out pin note: the above applies when the reload registers high-order 8 bits (n) = 02 16 and low-order 8 bits (m) = 02 16 and an external trigger (falling of tai in pin input signal) is selected. h h h l l l 1 0 timer ai interrupt request bit cleared to 0 when interrupt request is accepted or cleared by software. fi: frequency of count source (f 2 /f 4 , f 16 /f 32 , f 64 /f 128 , or f 512 /f 1024 ) the 8-bit prescaler counts the count source. the 8-bit pulse width modulator counts the 8-bit prescalers underflow signal. 8-bit prescalers underflow signal 1 / f i 5 (m+1) 5 (n) 1 / f i 5 (m+1)
timer a 7751 group users manual 5C47 5.6 pulse width modulation (pwm) mode fig. 5.6.7 operation example of 8-bit pulse width modulator (when counter value is updated during pulse output) h l h l (1 / f i ) 5 (m+1) 5 (2 8 C1) pwm pulse output from tai out pin count source tai in pins input signal (1 / f i ) 5 (m+1) 5 (2 8 C1) (1 / f i ) 5 (m + 1) 5 (2 8 C1) 00 16 prescaler's contents (hex.) 02 16 time stops counting. 01 16 counters contents (hex.) 04 16 0a 16 time when an arbitrary value is set to the timer ai register after setting 00 16 to it, the timing at which the pwm pulse level goes h depends on the timing at which the new value is set. 0002 16 is set to timer ai register. 0a02 16 is set to timer ai register. 0402 16 is set to timer ai register. restarts counting. note: the above applies when an external trigger (falling of tai in pins input signal) is selected. fi: frequency of count source (f 2 /f 4 , f 16 /f 32 , f 64 /f 128 , or f 512 /f 1024 ) m: contents of reload registers low-order 8 bits
timer a 7751 group users manual 5C48 5.6 pulse width modulation (pwm) mode [precautions when operating in pwm mode] 1. if the count start bit is cleared to 0 while outputting pwm pulses, the counter stops counting. when the tai out pin was outputting h level at that time, the output level becomes l and the timer ai interrupt request bit is set to 1. when the tai out pin was outputting l level, the output level does not change and the timer ai interrupt request does not occur. 2. when setting the timers operating mode in one of the followings, the timer ai interrupt request bit is set to 1. l when the pwm mode is selected after a reset l when the operating mode is switched from the timer mode to pwm mode l when the operating mode is switched from the event counter mode to the pwm mode therefore, when using the timer ai interrupt (interrupt request bit), be sure to clear the timer ai interrupt request bit to 0 after the above setting.
chapter 6 timer b 6.1 overview 6.2 block description 6.3 timer mode 6.4 event counter mode 6.5 pulse period/pulse width measurement mode
timer b 7751 group users manual 6C2 timer b consists of three counters (timers b0 to b2) each equipped with a 16-bit reload function. timers b0 to b2 have identical functions and operate independently with each other. 6.1 overview timer bi (i = 0 to 2) has three operating modes listed below. l timer mode the timer counts an internally generated count source. l event counter mode the timer counts an external signal. l pulse period/pulse width measurement mode the timer measures an external signals pulse period or pulse width. 6.2 block description figure 6.2.1 shows the block diagram of timer b. explanation of registers relevant to timer b is described below. 6.1 overview 6.2 block description fig. 6.2.1 block diagram of timer b f 2 /f 4 f 16 /f 32 f 64 /f 128 f 512 /f 1024 count source select bits timer mode pulse period/pulse width measurement mode polarity switching and edge pulse generating circuit event counter mode count start bit counter reset circuit data bus (odd) data bus (even) (low-order 8 bits) (high-order 8 bits) timer bi reload register (16) timer bi counter (16) timer bi interrupt request bit tbi in timer bi overflow flag
7751 group users manual timer b 6C3 6.2 block description 6.2.1 counter and reload register (timer bi register) each of timer bi counter and reload register consists of 16 bits and has the following functions. (1) functions in timer mode and event counter mode the counter down-counts each time count source is input. the reload register is used to store the initial value of the counter. when the counter underflows, the reload registers contents are reloaded into the counter. values are set to the counter and reload register by writing a value to the timer bi register. table 6.2.1 lists the memory assignment of the timer bi register. the value written into the timer bi register when the counting is not in progress is set to the counter and reload register. the value written into the timer bi register when the counting is in progress is set to only the reload register. in this case, the reload registers updated contents are transferred to the counter when the counter underflows next time. the counter value is read out by reading out the timer bi register. note: when reading and writing from/to the timer bi register, perform them in a unit of 16 bits. for more information about the value got by reading the timer bi register, refer to [precautions when operating in timer mode] and [precautions when operating in event counter mode]. (2) functions in pulse period/pulse width measurement mode the counter up-counts each time count source is input. the reload register is used to retain the pulse period or pulse width measurement result. when a valid edge is input to the tbi in pin, the counter value is transferred to the reload register. in this mode, the value got by reading the timer bi register is the reload registers contents, so that the measurement result is obtained. note: when reading from the timer bi register, perform it in a unit of 16 bits. timer bi register timer b0 register timer b1 register timer b2 register low-order byte address 50 16 address 52 16 address 54 16 high-order byte address 51 16 address 53 16 address 55 16 note : when reset, the contents of the timer bi reg- ister are undefined. table 6.2.1 memory assignment of timer bi registers
timer b 7751 group users manual 6C4 6.2.2 count start register this register is used to start and stop counting. each bit of this register corresponds each timer. figure 6.2.2 shows the structure of the count start register. 6.2 block description fig. 6.2.2 structure of count start register bit timer b2 count start bit timer b1 count start bit timer b0 count start bit timer a4 count start bit timer a3 count start bit timer a2 count start bit timer a1 count start bit timer a0 count start bit bit name at reset 0 0 0 0 0 0 0 0 rw functions b7 b6 b5 b4 b3 b2 b1 b0 count start register (address 40 16 ) 0 : stop counting 1 : start counting rw rw rw rw rw rw rw rw 0 1 2 3 4 5 6 7 : bits 0 to 4 are not used for timer b.
7751 group users manual timer b 6C5 6.2.3 timer bi mode register figure 6.2.3 shows the structure of the timer bi mode register. the operating mode select bits are used to select the operating mode of timer bi. bits 2 and 3 and bits 5 to 7 have different functions according to the operating mode. these bits are described in the paragraph of each operating mode. 6.2 block description fig. 6.2.3 structure of timer bi mode register nothing is assigned. these bits have different functions according to the operating mode. 1 operating mode select bits bit name functions b7 b6 b5 b4 b3 b2 b1 b0 timer bi mode register (i = 0 to 2) (addresses 5b 16 to 5d 16 ) 0 0 : timer mode 0 1 : event counter mode 1 0 : pulse period/pulse width measurement mode 1 1 : not selected b1 b0 bit 5 at reset rw 0 2 0 rw rw rw 6 7 note: bit 5 is ignored in the timer mode and event counter mode; its value is undefined at reading. 3 0 0 rw 0 C undefined 4 ro (note) undefined rw 0 rw 0 these bits have different functions according to the operating mode.
timer b 7751 group users manual 6C6 6.2.4 timer bi interrupt control register figure 6.2.4 shows the structure of the timer bi interrupt control register. for details about interrupts, refer to chapter 4. interrupts. 6.2 block description b7 b6 b5 b4 b3 b2 b1 b0 bit 7 to 4 interrupt request bit 2 1 0 bit name at reset 0 rw functions 0 0 0 : level 0 (interrupt disabled) 0 0 1 : level 1 low level 0 1 0 : level 2 0 1 1 : level 3 1 0 0 : level 4 1 0 1 : level 5 1 1 0 : level 6 1 1 1 : level 7 high level b2 b1 b0 0 : no interrupt request 1 : interrupt request interrupt priority level select bits 3 rw rw rw rw C undefined 0 0 0 nothing is assigned. timer bi interrupt control register (i = 0 to 2) (addresses 7a 16 to 7c 16 ) fig. 6.2.4 structure of timer bi interrupt control register (1) interrupt priority level select bits (bits 2 to 0) these bits select a timer bi interrupts priority level. when using timer bi interrupts, select priority levels 1 to 7. when the timer bi interrupt request occurs, its priority level is compared with the processor interrupt priority level (ipl), so that the requested interrupt is enabled only when its priority level is higher than the ipl. (however, this applies when the interrupt disable bit (i) = 0.) to disable timer bi interrupts, set these bits to 000 2 (level 0). (2) interrupt request bit (bit 3) this bit is set to 1 when the timer bi interrupt request occurs. this bit is automatically cleared to 0 when the timer bi interrupt request is accepted. this bit can be set to 1 or cleared to 0 by software.
7751 group users manual timer b 6C7 6.2.5 port p6 direction register timer bis input pins are shared with port p6. when using these pins as timer bis input pins, set the corresponding bits of the port p6 direction register to 0 to set these pins for the input mode. figure 6.2.5 shows the relationship between port p6 direction register and timer bis input pins. 6.2 block description fig. 6.2.5 relationship between port p6 direction register and timer bis input pins 0 1 2 3 4 5 6 7 ta4 out pin int 0 pin int 1 pin int 2 pin tb1 in pin tb0 in pin port p6 direction register (address 10 16 ) b1 b0 b2 b3 b4 b5 b6 b7 ta4 in pin tb2 in pin rw 0 0 0 0 0 0 0 0 : bits 0 to 4 are not used for timer b. corresponding pin name functions bit at reset 0: input mode 1: output mode when using these pins as timer bi's input pins, set the corresponding bits to "0." rw rw rw rw rw rw rw rw
timer b 6C8 7751 group users manual 6.3 timer mode 6.3 timer mode in this mode, the timer counts an internally generated count source. (refer to table 6.3.1.) figure 6.3.1 shows the structures of the timer bi mode register and timer bi register in the timer mode. table 6.3.1 specifications of timer mode item count source count operation count start condition count stop condition interrupt request occurrence timing tbi in pin function read from timer bi register write to timer bi register specifications f 2 /f 4 , f 16 /f 32 , f 64 /f 128 , or f 512 /f 1024 ?down-count ?when the counter underflows, reload registers contents are reloaded and counting continues. when count start bit is set to 1. when count start bit is cleared to 0. when the counter underflows. programmable i/o port counter value can be read out. l while counting is stopped when a value is written to the timer bi register, it is written to both reload register and counter. l while counting is in progress when a value is written to the timer bi register, it is written to only reload register. (transferred to counter at next reload time.)
timer b 7751 group users manual 6C9 6.3 timer mode fig. 6.3.1 structures of timer bi mode register and timer bi register in timer mode b7 b0 b7 b0 (b15) (b8) timer b0 register (addresses 51 16 , 50 16 ) timer b1 register (addresses 53 16 , 52 16 ) timer b2 register (addresses 55 16 , 54 16 ) rw 15 to 0 bit functions at reset these bits can be set to 0000 16 to ffff 16 . assuming that the set value = n, the counter divides the count source frequency by n + 1. when reading, the register indicates the counter value. undefined rw b7 b6 b5 b4 b3 b2 b1 b0 00 bit this bit is ignored in timer mode. nothing is assigned. bit name count source select bits functions at reset rw these bits are ignored in timer mode. operating mode select bits 1 0 0 : timer mode b1 b0 0 5 5 0 2 rw rw 3 rw rw timer bi mode register (i = 0 to 2) (addresses 5b 16 to 5d 16 ) 5 0 0 0 C undefined 4 undefined 5 6 7 0 0 : f 2 /f 4 0 1 : f 16 /f 32 1 0 : f 64 /f 128 1 1 : f 512 /f 1024 b7 b6 rw 0 rw 0 C
timer b 6C10 7751 group users manual 6.3 timer mode 6.3.1 setting for timer mode figure 6.3.2 shows an initial setting example for registers relevant to the timer mode. note that when using interrupts, set up to enable the interrupts. for details, refer to chapter 4. interrupts. fig. 6.3.2 initial setting example for registers relevant to timer mode b7 b0 count source select bits 0 0 : f 2 /f 4 0 1 : f 16 /f 32 1 0 : f 64 /f 128 1 1 : f 512 /f 1024 selecting timer mode and count source timer bi mode register (i = 0 to 2) (addresses 5b 16 to 5d 16 ) setting count start bit to 1 b7 b0 count start register (address 40 16 ) timer b0 count start bit timer b1 count start bit timer b2 count start bit b7 b6 setting interrupt priority level b7 b0 timer bi interrupt control register (i = 0 to 2) (addresses 7a 16 to 7c 16 ) interrupt priority level select bits when using interrupts, set these bits to level 1C7. when disabling interrupts, set these bits to level 0. 5 : it may be either 0 or 1. selection of timer mode note : the counter divides the count source by n + 1. setting divide ratio b7 b0 can be set to 0000 16 to ffff 16 (n). (b15) (b8) b7 b0 timer b0 register (addresses 51 16 , 50 16 ) timer b1 register (addresses 53 16 , 52 16 ) timer b2 register (addresses 55 16 , 54 16 ) 00 55 5 count starts
timer b 7751 group users manual 6C11 6.3 timer mode 6.3.2 count source in the timer mode, the count source select bits (bits 6 and 7 at addresses 5b 16 to 5d 16 ) select the count source. table 6.3.2 lists the count source frequency. table 6.3.2 count source frequency f(x in ) = 25 mhz clock source for peripheral devices select bit = 0 count source f 4 f 32 f 128 f 1024 f(x in ) = 40 mhz b6 0 1 0 1 count source select bits b7 0 0 1 1 frequency 6.25 mhz 781.25 khz 195.3125 khz 24.4141 khz clock source for peripheral devices select bit = 1 clock source for peripheral devices select bit = 0 count source f 4 f 32 f 128 f 1024 count source f 2 f 16 f 64 f 512 frequency 12.5 mhz 1.5625 mhz 390.625 khz 48.8281 khz frequency 10 mhz 1.25 mhz 312.5 khz 39.0625 khz clock source for peripheral devices select bit : bit 2 at address 5f 16
timer b 6C12 7751 group users manual 6.3 timer mode 6.3.3 operation in timer mode when the count start bit is set to 1, the counter starts counting of the count source. when the counter underflows, the reload registers contents are reloaded and counting continues. a the timer bi interrupt request bit is set to 1 when the counter underflows in . the interrupt request bit remains set to 1 until the interrupt request is accepted or the interrupt request bit is cleared to 0 by software. figure 6.3.3 shows an example of operation in the timer mode. stops counting. restarts counting. ffff 16 n 0000 16 time count start bit timer bi interrupt request bit 1 1 counter contents (hex.) n = reload registers contents cleared to 0 when interrupt request is accepted or cleared by software. set to 1 by software. starts counting. set to 1 by software. 0 0 1 / f i 5 (n+1) fi = frequency of count source (f 2 /f 4 , f 16 /f 32 , f 64 /f 128 , f 512 /f 1024 ) cleared to 0 by software. fig. 6.3.3 example of operation in timer mode
timer b 7751 group users manual 6C13 6.3 timer mode [precautions when operating in timer mode] by reading the timer bi register, the counter value can be read out at any timing while counting is in progress. however, if the timer bi register is read at the reload timing shown in figure 6.3.4, the value ffff 16 is read out. when reading the timer bi register after setting a value to the register while counting is not in progress and before the counter starts counting, the set value can be read out correctly. fig. 6.3.4 reading timer bi register 2 1 0 n n C 1 counter value (hex.) 2 1 0 ffff n C 1 read value (hex.) reload time n = reload registers contents
timer b 6C14 7751 group users manual 6.4 event counter mode 6.4 event counter mode in this mode, the timer counts an external signal. (refer to table 6.4.1.) figure 6.4.1 shows the structures of the timer bi mode register and the timer bi register in the event counter mode. table 6.4.1 specifications of event counter mode item count source count operation count start condition count stop condition interrupt request occurrence timing tbi in pin function read from timer bi register write to timer bi register specifications ?external signal input to the tbi in pin ? the count sources valid edge can be selected from the falling edge, the rising edge, or both of the falling and rising edges by software. ?down-count ?when the counter underflows, reload registers contents are reloaded and counting continues. when count start bit is set to 1. when count start bit is cleared to 0. when the counter underflows. count source input counter value can be read out. l while counting is stopped when a value is written to the timer bi register, it is written to both reload register and counter. l while counting is in progress when a value is written to the timer bi register, it is written to only reload register. (transferred to counter at next reload time.)
timer b 7751 group users manual 6C15 6.4 event counter mode fig. 6.4.1 structures of timer bi mode register and timer bi register in event counter mode b7 b0 b7 b0 (b15) (b8) timer b0 register (addresses 51 16 , 50 16 ) timer b1 register (addresses 53 16 , 52 16 ) timer b2 register (addresses 55 16 , 54 16 ) rw 15 to 0 bit functions at reset rw these bits can be set to 0000 16 to ffff 16 . assuming that the set value = n, the counter divides the count source frequency by n + 1. when reading, the register indicates the counter value. undefined 0 0 : count at falling edge of external signal 0 1 : count at rising edge of external signal 1 0 : counts at both falling and rising edges of external signal 1 1 : not selected b7 b6 b5 b4 b3 b2 b1 b0 01 bit count polarity select bit bit name these bits are ignored in event counter mode. this bit is ignored in event counter mode. 7 functions at reset 0 0 0 undefined rw operating mode select bits 1 0 1 : event counter mode b1 b0 0 0 0 55 0 2 rw rw 3 4 5 6 rw rw rw rw timer bi mode register (i = 0 to 2) (addresses 5b 16 to 5d 16 ) b3 b2 nothing is assigned. undefined 5
timer b 6C16 7751 group users manual 6.4 event counter mode 6.4.1 setting for event counter mode figure 6.4.2 shows an initial setting example for registers relevant to the event counter mode. note that when using interrupts, set up to enable the interrupts. for details, refer to section chapter 4. interrupts. fig. 6.4.2 initial setting example for registers relevant to event counter mode note : the counter divides the count source by n + 1. setting divide ratio b7 b0 can be set to 0000 16 to ffff 16 (n). (b15) (b8) b7 b0 timer b0 register (addresses 51 16 , 50 16 ) timer b1 register (addresses 53 16 , 52 16 ) timer b2 register (addresses 55 16 , 54 16 ) b7 b0 0 0 : counts at falling of external signal. 0 1 : counts at rising of external signal. 1 0 : counts at both of falling and rising of external signal. 1 1 : not selected. 01 selecting event counter mode and count polarity timer bi mode register (i = 0 to 2) (addresses 5b 16 to 5d 16 ) setting count start bit to 1 b7 b0 count start register (address 40 16 ) timer b0 count start bit timer b1 count start bit timer b2 count start bit b3 b2 setting interrupt priority level b7 b0 timer bi interrupt control register (i = 0 to 2) (addresses 7a 16 to 7c 16 ) interrupt priority level select bits when using interrupts, set these bits to level 1C7. when disabling interrupts, set these bits to level 0. setting port p6 direction register b7 b0 port p6 direction register (address 10 16 ) clear the corresponding bit to 0. tb0 in pin tb1 in pin tb2 in pin 5 5 : it may be either 0 or 1. selection of event counter mode count polarity select bits 5 5 count starts
timer b 7751 group users manual 6C17 6.4 event counter mode 6.4.2 operation in event counter mode when the count start bit is set to 1, the counter starts counting of the count source. the counter counts the count sources valid edges. a when the counter underflows, the reload registers contents are reloaded and counting continues. ? the timer bi interrupt request bit is set to 1 when the counter underflows in a . the interrupt request bit remains set to 1 until the interrupt request is accepted or the interrupt request bit is cleared to 0 by software. figure 6.4.3 shows an example of operation in the event counter mode. stops counting. restarts counting . ffff 16 n 0000 16 time count start bit timer bi interrupt request bit 1 1 counter contents (hex.) n = reload registers contents cleared to 0 when interrupt request is accepted or cleared by software. set to 1 by software. starts counting. cleared to 0 by software. 0 0 set to 1 by software. fig. 6.4.3 example of operation in event counter mode
timer b 6C18 7751 group users manual 6.4 event counter mode [precautions when operating in event counter mode] by reading the timer bi register, the counter value can be read out at any timing while counting is in progress. however, if the timer bi register is read at the reload timing shown in figure 6.4.4, the value ffff 16 is read out. when reading the timer bi register after setting a value to the register while counting is not in progress and before the counter starts counting, the set value can be read out correctly. fig. 6.4.4 reading timer bi register 2 1 0 n n C 1 counter value (hex.) 2 1 0 ffff n C 1 read value (hex.) reload time n = reload registers contents
timer b 7751 group users manual 6C19 6.5 pulse period/pulse width measurement mode 6.5 pulse period/pulse width measurement mode in these mode, the timer measures an external signals pulse period or pulse width. (refer to table 6.5.1.) figure 6.5.1 shows the structures of the timer bi mode register and timer bi register in the pulse period/ pulse width measurement mode. l pulse period measurement the timer measures the pulse period of the external signal that is input to the tbi in pin. l pulse width measurement the timer measures the pulse width (l level and h level widths) of the external signal that is input to the tbi in pin. table 6.5.1 specifications of pulse period/pulse width measurement mode item count source count operation count start condition count stop condition interrupt request occurrence timing tbi in pin function read from timer bi register write to timer bi register specifications f 2 /f 4 , f 16 /f 32 , f 64 /f 128 , or f 512 /f 1024 l up-count l counter value is transferred to reload register at valid edge of mea- surement pulse, and counting continues after clearing the counter value to 0000 16 . when count start bit is set to 1. when count start bit is cleared to 0. l when valid edge of measurement pulse is input ( note 1 ). l when counter overflows (timer bi overflow flag ] is set to 1 simultaneously). measurement pulse input the value got by reading timer bi register is the reload registers contents, measurement result ( note 2 ). impossible. timer bi overflow flag ] : the bit used to identify the source of an interrupt request occurrence. notes 1: this interrupt request does not occur when the first valid edge is input after the timer starts counting. 2: the value read out from the timer bi register is undefined until the second valid edge is input after the timer starts counting.
timer b 6C20 7751 group users manual 6.5 pulse period/pulse width measurement mode fig. 6.5.1 structures of timer bi mode register and timer bi register in pulse period/pulse width measurement mode b7 b0 b7 b0 (b15) (b8) timer b0 register (addresses 51 16 , 50 16 ) timer b1 register (addresses 53 16 , 52 16 ) timer b2 register (addresses 55 16 , 54 16 ) functions bit at reset rw 15 to 0 the measurement result of pulse period or pulse width is read out. undefined ro measurement mode select bits 1 operating mode select bits bit name functions b7 b6 b5 b4 b3 b2 b1 b0 timer bi mode register (i = 0 to 2) (addresses 5b 16 to 5d 16 ) 1 0 : pulse period/pulse width measurement mode 7 0 0 : f 2 /f 4 0 1 : f 16 /f 32 1 0 : f 64 /f 128 1 1 : f 512 /f 1024 b7 b6 count source select bits b1 b0 b3 b2 nothing is assigned. 0 1 0 0 : pulse period measurement (interval between falling edges of measurement pulse) 0 1 : pulse period measurement (interval between rising edges of measurement pulse) 1 0 : pulse width measurement (interval from falling edge to rising edge, and from rising edge to falling edge of measurement pulse) 1 1 : not selected bit at reset undefined 0 rw 4 0 2 3 6 rw rw rw rw C rw rw 5 0 0 0 timer bi overflow flag (note) 0 : no overflow 1 : overflow undefined ro 0 0 note: the timer bi overflow flag is cleared to 0 by writing to the timer bi mode register with the count start bit = 1.
timer b 7751 group users manual 6C21 6.5 pulse period/pulse width measurement mode 6.5.1 setting for pulse period/pulse width measurement mode figure 6.5.2 shows an initial setting example for registers relevant to the pulse period/pulse width measurement mode. note that when using interrupts, set up to enable the interrupts. for details, refer to chapter 4. interrupts.
timer b 6C22 7751 group users manual 6.5 pulse period/pulse width measurement mode fig. 6.5.2 initial setting example for registers relevant to pulse period/pulse width measurement mode count starts b7 b0 measurement mode select bits 10 selecting pulse period/pulse width measurement mode and each function timer bi mode register (i = 0 to 2) (addresses 5b 16 to 5d 16 ) setting count start bit to 1 b7 b0 count start register (address 40 16 ) timer b0 count start bit timer b1 count start bit timer b2 count start bit b3 b2 count source select bits b7 b6 timer bi overflow flag (note) 0: no overflow 1: overflow setting port p6 direction register b7 b0 port p6 direction register (address 10 16 ) clear the corresponding bit to 0. tb0 in pin tb1 in pin tb2 in pin 0 0 : pulse period measurement (interval between falling edges of measured pulse) 0 1 : pulse period measurement (interval between rising edges of measured pulse) 1 0 : pulse width measurement 1 1 : not selected. 0 0 : f 2 /f 4 0 1 : f 16 /f 32 1 0 : f 64 /f 128 1 1 : f 512 /f 1024 note: the timer bi overflow flag is a read-only bit. this bit is undefined after reset. this bit is cleared to 0 by writing to the timer bi mode register with the count start bit = 1. setting interrupt priority level b7 b0 timer bi interrupt control register (i = 0 to 2) (addresses 7a 16 to 7c 16 ) interrupt priority level select bits when using interrupts, set these bits to level 1C7. when disabling interrupts, set these bits to level 0. selection of pulse period/pulse width measurement mode
timer b 7751 group users manual 6C23 6.5 pulse period/pulse width measurement mode 6.5.2 count source in the pulse period/pulse width measurement mode, the count source select bits (bits 6 and 7 at addresses 5b 16 to 5d 16 ) select the count source. table 6.5.2 lists the count source frequency. table 6.5.2 count source frequency f(x in ) = 25 mhz clock source for peripheral devices select bit = 0 count source f 4 f 32 f 128 f 1024 f(x in ) = 40 mhz b6 0 1 0 1 count source select bits b7 0 0 1 1 frequency 6.25 mhz 781.25 khz 195.3125 khz 24.4141 khz clock source for peripheral devices select bit = 1 clock source for peripheral devices select bit = 0 count source f 4 f 32 f 128 f 1024 count source f 2 f 16 f 64 f 512 frequency 12.5 mhz 1.5625 mhz 390.625 khz 48.8281 khz frequency 10 mhz 1.25 mhz 312.5 khz 39.0625 khz clock source for peripheral devices select bit : bit 2 at address 5f 16
timer b 6C24 7751 group users manual 6.5 pulse period/pulse width measurement mode 6.5.3 operation in pulse period/pulse width measurement mode when the count start bit is set to 1, the counter starts counting of the count source. the counter value is transferred to the reload register when an valid edge of the measurement pulse is detected. (refer to section (1) pulse period/pulse width measurement. ) a the counter value is cleared to 0000 16 after the transfer in , and the counter continues counting. ? the timer bi interrupt request bit is set to 1 when the counter value is cleared to 0000 16 in a ( note ). the interrupt request bit remains set to 1 until the interrupt request is accepted or the interrupt request bit is cleared to 0 by software. ? the timer repeats operations to ? above. note: the timer bi interrupt request does not occur when the first valid edge is input after the timer starts counting. (1) pulse period/pulse width measurement the measurement mode select bits (bits 2 and 3 at addresses 5b 16 to 5d 16 ) specify whether the pulse period of an external signal is measured or its pulse width is done. table 6.5.3 lists the relationship between the measurement mode select bits and the pulse period/pulse width measurements. make sure that the measurement pulse interval from the falling to the rising, and from the rising to the falling are two cycles of the count source or more. additionally, use software to identify whether the measurement result indicates the h level or the l level width. table 6.5.3 relationship between measurement mode select bits and pulse period/pulse width measurements b3 0 0 1 1 pulse period/pulse width measurement pulse period measurement pulse width measurement not selected measurement interval (valid edges) from falling to falling (falling) from rising to rising (rising) from falling to rising, and from rising to falling (falling and rising) b2 0 1 0 1
timer b 7751 group users manual 6C25 6.5 pulse period/pulse width measurement mode (2) timer bi overflow flag the timer bi interrupt request occurs when the measurement pulses valid edge is input or the counter overflows. the timer bi overflow flag is used to identify the cause of the interrupt request, that is, whether it is an overflow occurrence or an effective edge input. the timer bi overflow flag is set to 1 by an overflow. accordingly, the cause of the interrupt request occurrence is identified by checking the timer bi overflow flag in the interrupt routine. when a value is written to the timer bi mode register with the count start bit = 1, the timer bi overflow flag is cleared to 0 at the next count timing of the count source the timer bi overflow flag is a read-only bit. use the timer bi interrupt request bit to detect the overflow timing. do not use the timer bi overflow flag to do that. figure 6.5.3 shows the operation during pulse period measurement. figure 6.5.4 shows the operation during pulse width measurement. fig. 6.5.3 operation during pulse period measurement count source measurement pulse timing at which counter is cleared to 0000 16 1 h 1 note: the above applies when measurement is performed for an interval from one falling to the next falling of the measurement pulse. reload register counter transfer timing l 0 0 count start bit 1 0 counter is initialized by completion of measurement. counter overflow. cleared to 0 when interrupt request is accepted or cleared by software. timer bi interrupt request bit timer bi overflow flag transferred (undefined value) transferred (measured value)
timer b 6C26 7751 group users manual 6.5 pulse period/pulse width measurement mode fig. 6.5.4 operation during pulse width measurement measurement pulse h count source timing at which counter is cleared to 0000 16 1 1 l 0 0 1 0 count start bit timer bi interrupt request bit timer bi overflow flag reload register counter transfer timing counter is initialized by completion of measurement. counter overflow. transferred (measured value) transferred (measured value) transferred (measured value) transferred (undefined value) cleared to 0 when interrupt request is accepted or cleared by software.
timer b 7751 group users manual 6C27 6.5 pulse period/pulse width measurement mode [precautions when operating in pulse period/pulse width measurement mode] 1. the timer bi interrupt request occurs by the following two causes: l input of measured pulses valid edge l counter overflow when the overflow is the cause of the interrupt request occurrence, the timer bi overflow flag is set to 1. 2. after reset, the timer bi overflow flag is undefined. when writing to the timer bi mode register with the count start bit = 1, this flag can be cleared to 0 at the next count timing of the count source. 3. an undefined value is transferred to the reload register when the first valid edge is input after the counter starts counting. in this case, the timer bi interrupt request does not occur. 4. the counter value at start of counting is undefined. accordingly, the timer bi interrupt request may occur by the overflow immediately after the counter starts counting. 5. if the contents of the measurement mode select bits are changed after the counter starts counting, the timer bi interrupt request bit is set to 1. when writing the same value which has been set yet to the measurement mode select bits, the timer bi interrupt request bit is not changed, that is, the bit retains the state. 6. if the input signal to the tbi in pin is affected by noise, etc., the counter may not perform the exact measurement. we recommend to verify, by software, that the measurement values are within a constant range.
timer b 6C28 7751 group users manual 6.5 pulse period/pulse width measurement mode memorandum
7.1 overview 7.2 block description 7.3 clock synchronous serial i/o mode 7.4 clock asynchronous serial i/o (uart) mode chapter 7 serial i/o
serial i/o 7751 group users manual 7C2 this chapter describes the serial i/o. the serial i/o consists of 2 channels: uart0 and uart1. they each have a transfer clock generating timer for the exclusive use of them and can operate independently. uart0 and uart1 have the same functions. 7.1 overview uarti (i = 0 and 1) has the following 2 operating modes: l clock synchronous serial i/o mode transmitter and receiver use the same clock as the transfer clock. transfer data has the length of 8 bits. l clock asynchronous serial i/o (uart) mode transfer rate and transfer data format can arbitrarily be set. the user can select a 7-bit, 8-bit, or 9-bit length as the transfer data length. 7.1 overview l clock synchronous serial i/o mode transfer data length of 8 bits (lsb first) transfer data length of 8 bits (msb first) l uart mode transfer data length of 7 bits transfer data length of 8 bits transfer data length of 9 bits fig. 7.1.1 transfer data formats in each operating mode
serial i/o 7751 group users manual 7C3 7.2 block description figure 7.2.1 shows the block diagram of serial i/o. registers relevant to serial i/o are described below. fig. 7.2.1 block diagram of serial i/o 7.2 block description rxd i data bus (odd) data bus (even) 0000000 uarti receive register uarti receive buffer register uarti transmit buffer register receive control circuit transmit control circuit 1 / (n+1) 1/16 1/16 1/2 brgi clock synchronous (internal clock selected) uart clock synchronous uart clock synchronous (internal clock selected) clock synchronous (external clock selected) data bus (odd) data bus (even) txd i transfer clock transfer clock clk i brg count source select bits cts i / rts i uarti transmit register n: values set in uarti baud rate register (brgi) clock synchronous d 8 d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 f 2 /f 4 f 16 /f 32 f 64 /f 128 f 512 /f 1024 d 8 d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 bit converter bit converter
serial i/o 7751 group users manual 7C4 7.2.1 uarti transmit/receive mode register figure 7.2.2 shows the structure of uarti transmit/receive mode register. the serial i/o mode select bits is used to select uartis operating mode. bits 4 to 6 are described in the section 7.4.2 transfer data format , and bit 7 is done in the section 7.4.8 sleep mode. 7.2 block description fig. 7.2.2 structure of uarti transmit/receive mode register b7 b6 b5 b4 b3 b2 b1 b0 bit 4 2 1 0 bit name at reset 0 rw functions b2 b1 b0 3 7 6 5 rw rw rw rw rw rw rw rw 0 0 0 0 serial i/o mode select bits 0 0 0 : serial i/o disabled (p8 functions as a programmable i/o port.) 0 0 1 : clock synchronous serial i/o mode 0 1 0 : not selected 0 1 1 : not selected 1 0 0 : uart mode (transfer data length = 7 bits) 1 0 1 : uart mode (transfer data length = 8 bits) 1 1 0 : uart mode (transfer data length = 9 bits) 1 1 1 : not selected sleep select bit (valid in uart mode) ( note ) parity enable bit (valid in uart mode) ( note ) odd/even parity select bit (valid in uart mode when parity enable bit is 1) ( note ) stop bit length select bit (valid in uart mode) ( note ) internal/external clock select bit uart0 transmit/receive mode register (address 30 16 ) uart1 transmit/receive mode register (address 38 16 ) note: bits 4 to 6 are ignored in the clock synchronous serial i/o mode. (they may be either 0 or 1.) additionally, fix bit 7 to 0. 0 : odd parity 1 : even parity 0 : parity disabled 1 : parity enabled 0 : sleep mode cleared (ignored) 1 : sleep mode selected 0 : internal clock 1 : external clock 0 : one stop bit 1 : two stop bits 0 0 0
serial i/o 7751 group users manual 7C5 (1) internal/external clock select bit (bit 3) [clock synchronous serial i/o mode] by clearing this bit to 0 in order to select an internal clock, the clock which is selected with the brg count source select bits (bits 0 and 1 at addresses 34 16 , 3c 16 ) becomes the count source of brgi (described later). the brgi output of which frequency is divided by 2 becomes the transfer clock. additionally, the transfer clock is output from the clk i pin. by setting this bit to 1 in order to select an external clock, the clock input to the clk i pin becomes the transfer clock. [uart mode] by clearing this bit to 0 in order to select an internal clock, the clock which is selected with the brg count source select bits (bits 0 and 1 at addresses 34 16 , 3c 16 ) becomes the count source of the brgi (described later). then, the clk i pin functions as a programmable i/o port. by setting this bit to 1 in order to select an external clock, the clock input to the clk i pin becomes the count source of brgi. always in the uart mode, the brgi output of which frequency is divided by 16 is the transfer clock. 7.2 block description
serial i/o 7751 group user?s manual 7e6 7.2 block description 7.2.2 uarti transmit/receive control register 0 figure 7.2.3 shows the structure of uarti transmit/receive c ontrol register 0. for bits 0 and 1, refer to 7.2.1 (1) internal/external clock select bit. for bit 7, refer to 7.2.2 transfer data format. fig. 7.2.3 structure of uarti transmit/receive control regis ter 0 (1) ____ ____ cts/rts select bit (bit 2) ____ ____ by clearing this bit to 0 in order to select the cts function, pins p8 0 and p8 4 function as cts input pins, and the input signal of l level to these pins become s one of the transmission conditions. ____ ____ by setting this bit to 1 in order to select the rts functi on, pins p8 0 and p8 4 become rts output ____ pins. when the receive enable bit (bit 2 at addresses 35 16 , 3d 16 ) is 0 (reception disabled), the rts output pin outputs h level. the output level of this pin becomes l when the receive en able bit is set to 1. it becomes h when reception starts and it becomes l when reception is c ompleted. (2) transmit register empty flag (bit 3) this flag is cleared to 0 when the uarti transmit buffer r egister?s contents are transferred to the uarti transmit register. when transmission is completed and the uarti transmit register becomes empty, this flag is set to 1. cts/rts select bit bit 1 brg count source select bits bit name at reset rw functions b7 b6 b5 b4 b3 b2 b1 b0 0 0 : f 2 / f 4 0 1 : f 16 / f 32 1 0 : f 64 / f 128 1 1 : f 512 / f 1024 uart0 transmit/receive control register 0 (address 34 16 ) uart1 transmit/receive control register 0 (address 3c 16 ) b1 b0 0 : cts function selected. 1 : rts function selected. transmit register empty flag 0 : data present in transmit register. (during transmitting) 1 : no data present in transmit register. (transmitting completed) 1 0 0 0 7 0 : lsb (least significant bit) first 1 : msb (most significant bit) first 0 transfer format select bit (used in clock synchronous serial i/o mode) (note) 0 2 rw rw ro 3 rw 6 to 4 nothing is assigned. undefined e rw note: fix bit 7 to 0 in the uart mode or when serial i/o is ign ored.
serial i/o 7751 group users manual 7C7 7.2 block description 7.2.3 uarti transmit/receive control register 1 figure 7.2.4 shows the structure of uarti transmit/receive control register 1. for bits 4 to 7, refer to each operation modes description. fig. 7.2.4 structure of uarti transmit/receive control register 1 bit bit name at reset 5 framing error flag (valid in uart mode) 0 0 : no framing error 1 : framing error detected rw functions b7 b6 b5 b4 b3 b2 b1 b0 uart0 transmit/receive control register 1 (address 35 16 ) uart1 transmit/receive control register 1 (address 3d 16 ) notes 1: bit 4 is cleared to 0 when clearing the receive enable bit to 0. bits 5 and 6 are cleared to 0 when one of the following is performed: ?clearing the receive enable bit to 0. ?reading the low-order byte of the uarti receive buffer register (addresses 36 16 , 3e 16 ) out . bit 7 is cleared to 0 when all of bits 4 to 6 become 0. 2: bits 5 to 7 are ignored in the clock synchronous serial i/o mode. 0 transmit enable bit 0 0 : transmission disabled 1 : transmission enabled 1 transmit buffer empty flag 1 0 : data present in transmit buffer register. 1 : no data present in transmit buffer register. 2 receive enable bit 0 0 : reception disabled 1 : reception enabled 3 receive complete flag 0 0 : no data present in receive buffer register. 1 : data present in receive buffer register. 4 overrun error flag 0 0 : no overrun error 1 : overrun error detected 6 parity error flag (valid in uart mode) 0 0 : no parity error 1 : parity error detected 7 error sum flag (valid in uart mode) 0 0 : no error 1 : error detected (notes 1, 2) (notes 1, 2) (notes 1, 2) (note 1) rw ro rw ro ro ro ro ro
serial i/o 7751 group users manual 7C8 (1) transmit enable bit (bit 0) by setting this bit to 1, uarti enters the transmission enable state. by clearing this bit to 0 during transmission, uarti enters the transmission disable state after the transmission which is performed at that time is completed. (2) transmit buffer empty flag (bit 1) this flag is set to 1 when data set in the uarti transmit buffer register is transferred from the uarti transmit buffer register to the uarti transmit register. this flag is cleared to 0 when data is set in the uarti transmit buffer register. (3) receive enable bit (bit 2) by setting this bit to 1, uarti enters the reception enable state. by clearing this bit to 0 during reception, uarti quits the reception then and enters the reception disable state. (4) receive complete flag (bit 3) this flag is set to 1 when data is ready in the uarti receive register and that is transferred to the uarti receive buffer register (i.e., when reception is completed). this flag is cleared to 0 when the low-order byte of the uarti receive buffer register is read out or when the receive enable bit (bit 2) is cleared to 0. 7.2 block description
serial i/o 7751 group users manual 7C9 7.2.4 uarti transmit register and uarti transmit buffer register figure 7.2.5 shows the block diagram of transmit section; figure 7.2.6 shows the structure of uarti transmit buffer register. 7.2 block description fig. 7.2.6 structure of uarti transmit buffer register fig. 7.2.5 block diagram of transmit section sp sp par 0 2sp 1sp uart 7-bit uart 8-bit uart 7-bit uart 9-bit uart clock sync. clock sync. clock sync. data bus (even) data bus (odd) txd i uarti transmit register parity enabled parity disabled d 8 d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 sp : stop bit par : parity bit uarti transmit buffer register 8-bit uart 9-bit uart bit converter b7 b0 bit 8 to 0 at reset undefined rw functions wo b7 b0 (b15) (b8) 15 to 9 C undefined uart0 transmit buffer register (addresses 33 16 , 32 16 ) uart1 transmit buffer register (addresses 3b 16 , 3a 16 ) nothing is assigned. transmit data is set.
serial i/o 7751 group users manual 7C10 the uarti transmit buffer register is used to set transmit data. set the transmit data into the low-order byte of this register when operating in the clock synchronous serial i/o mode or when a 7-bit or 8-bit length of transfer data is selected in the uart mode. when a 9-bit length of transfer data is selected in the uart mode, set the transmit data into the uarti transmit buffer register as follows: ?bit 8 of the transmit data into bit 0 of high-order byte of this register. ?bits 7 to 0 of the transmit data into the low-order byte of this register. the transmit data which is set in the uarti transmit buffer register is transferred to the uarti transmit register when the transmission conditions are satisfied, and then it is output from the txd i pin synchronously with the transfer clock. the uarti transmit buffer register becomes empty when the data which is set in the uarti transmit buffer register is transferred to the uarti transmit register. accordingly, the user can set next transmit data. when selecting the msb first in the clock synchronous serial i/o mode, the data of which bit position was reversed is written, as a transmit data, into the uarti transmit buffer register. (refer to section 7.3.2 transfer data format. ) transmission operation itself is the same whichever format is selected, lsb first or msb first. when quitting the transmission which is in progress and setting the uarti transmit buffer register again, follow the procedure described bellow: clear the serial i/o mode select bits (bits 2 to 0 at addresses 30 16 , 38 16 ) to 000 2 (serial i/o disabled). set the serial i/o mode select bits again. a set the transmit enable bit (bit 0 at addresses 35 16 , 3d 16 ) to 1 (transmission enabled) and set transmit data in the uarti transmit buffer register. 7.2 block description
serial i/o 7751 group users manual 7C11 7.2.5 uarti receive register and uarti receive buffer register figure 7.2.7 shows the block diagram of receive section; figure 7.2.8 shows the structure of uarti receive buffer register. 7.2 block description fig. 7.2.8 structure of uarti receive buffer register fig. 7.2.7 block diagram of receive section clock sync. sp sp par 2sp 1sp uart 0 0 0 0 0 0 0 rxd i d 8 d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 sp : stop bit par : parity bit 8-bit uart 9-bit uart 7-bit uart 9-bit uart clock sync. clock sync. 7-bit uart 8-bit uart data bus (even) data bus (odd) uarti receive register parity enabled parity disabled uarti receive buffer register bit converter b7 b0 bit 8 to 0 at reset undefined rw functions ro b7 b0 (b15) (b8) 15 to 9 C uart0 receive buffer register (addresses 37 16 , 36 16 ) uart1 receive buffer register (addresses 3f 16 , 3e 16 ) nothing is assigned. the value is 0 at reading. receive data is read out from here. 0
serial i/o 7751 group users manual 7C12 the uarti receive register is used to convert serial data which is input to the rxd i pin into parallel data. this register takes in the input signal to the rxd i pin synchronously with the transfer clock, one bit at a time. the uarti receive buffer register is used to read out receive data. when reception is completed, receive data which is taken in the uarti receive register is automatically transferred to the uarti receive buffer register. the contents of uarti receive buffer register is updated when the next data is ready before reading out the data which has been transferred to the uarti receive buffer register (i.e., an overrun error occurs). when selecting the msb first in the clock synchronous serial i/o mode, bit position of data in the uarti receive buffer register is reversed, and then the data of which bit position was reversed is read out, as receive data. (refer to section 7.3.2 transfer data format. ) reception operation itself is the same whichever format is selected, lsb first or msb first. the uarti receive buffer register is initialized by setting the receive enable bit (bit 2 at addresses 35 16 , 3d 16 ) to 1 after clearing it to 0. figure 7.2.9 shows the contents of uarti receive buffer register when reception is completed. 7.2 block description fig. 7.2.9 contents of uarti receive buffer register when reception is completed b7 b0 b7 b0 0 000000 0 000000 0 000000 receive data (9 bits) receive data (8 bits) receive data (7 bits) in uart mode (transfer data length : 9 bits) in clock synchronous serial i/o mode in uart mode (transfer data length : 8 bits) in uart mode (transfer data length : 7 bits) same value as bit 7 in low-order byte same value as bit 6 in low-order byte high-order byte (addresses 37 16 , 3f 16 ) low-order byte (addresses 36 16 , 3e 16 )
serial i/o 7751 group users manual 7C13 7.2.6 uarti baud rate register (brgi) the uarti baud rate register (brgi) is an 8-bit timer exclusively used for uarti to generate a transfer clock. it has a reload register. assuming that a value set in the brgi is n (n = 00 16 to ff 16 ), the brgi divides the count source frequency by n + 1. in the clock synchronous serial i/o mode, the brgi is valid when an internal clock is selected, and a clock of which frequency is the brgi outputs frequency divided by 2 becomes the transfer clock. in the uart mode, the brgi is always valid, and a clock of which frequency is the brgi outputs frequency divided by 16 becomes the transfer clock. the data which is written to the addresses 31 16 and 39 16 is written to both the timer register and the reload register whether transmission/reception is stopped or in progress. accordingly, writing to their addresses, perform it while that is stopped. figure 7.2.10 shows the structure of the uarti baud rate register (brgi); figure 7.2.11 shows the block diagram of transfer clock generating section. 7.2 block description fig. 7.2.11 block diagram of transfer clock generating section brgi 1/2 transmit control circuit receive control circuit transfer clock for transmit operation transfer clock for receive operation transmit control circuit receive control circuit transfer clock for transmit operation transfer clock for receive operation brgi 1/16 f i : clock selected by brg count source select bits (f 2 /f 4 , f 16 /f 32 , f 64 /f 128 , or f 512 /f 1024 ) f ext : clock input to clk i pin (external clock) 1/16 f i f ext f ext f i b7 b0 uart0 baud rate register (address 31 16 ) uart1 baud rate register (address 39 16 ) functions bit at reset rw 7 to 0 can be set to 00 16 to ff 16 . assuming that the set value = n, brgi divides the count source frequency by n + 1. undefined wo fig. 7.2.10 structure of uarti baud rate register (brgi)
serial i/o 7751 group users manual 7C14 7.2.7 uarti transmit interrupt control and uarti receive interrupt control registers when using uarti, 2 types of interrupts, which are uarti transmit and uarti receive interrupts, can be used. each interrupt has its corresponding interrupt control register. figure 7.2.12 shows the structure of uarti transmit interrupt control and uarti receive interrupt control registers. for details about interrupts, refer to chapter 4. interrupts. 7.2 block description fig. 7.2.12 structure of uarti transmit interrupt control and uarti receive interrupt control registers b7 b6 b5 b4 b3 b2 b1 b0 uart0 transmit interrupt control register (address 71 16 ) uart0 receive interrupt control register (address 72 16 ) uart1 transmit interrupt control register (address 73 16 ) uart1 receive interrupt control register (address 74 16 ) bit 7 to 4 interrupt request bit 2 1 0 bit name at reset 0 rw functions 0 0 0 : level 0 (interrupt disabled) 0 0 1 : level 1 low level 0 1 0 : level 2 0 1 1 : level 3 1 0 0 : level 4 1 0 1 : level 5 1 1 0 : level 6 1 1 1 : level 7 high level b2 b1 b0 0 : no interrupt request 1 : interrupt request interrupt priority level select bits 3 rw rw rw rw C undefined 0 0 0 nothing is assigned.
serial i/o 7751 group users manual 7C15 7.2 block description (1) interrupt priority level select bits (bits 0 to 2) these bits select the priority level of the uarti transmit interrupt or uarti receive interrupt. when using uarti transmit/receive interrupt, select priority levels 1 to 7. when the uarti transmit/receive interrupt request occurs, its priority level is compared with the processor interrupt priority level (ipl), so that the requested interrupt is enabled only when its priority level is higher than the ipl. (however, this applies when the interrupt disable flag (i) = 0.) to disable the uarti transmit/receive interrupt, set these bits to 000 2 (level 0). (2) interrupt request bit (bit 3) the uarti transmit interrupt request bit is set to 1 when data is transferred from the uarti transmit buffer register to the uarti transmit register. the uarti receive interrupt request bit is set to 1 when data is transferred from the uarti receive register to the uarti receive buffer register. however, when an overrun error occurs, it does not change. each interrupt request bit is automatically cleared to 0 when its corresponding interrupt request is accepted. this bit can be set to 1 or 0 by software.
serial i/o 7751 group users manual 7C16 7.2 block description 7.2.8 port p8 direction register i/o pins of uarti are shared with port p8. when using pins p8 2 and p8 6 as serial data input pins (rxd i ), set the corresponding bits of the port p8 direction register to 0 to set these pins for the input mode. when ____ ____ using pins p8 0 , p8 1 , p8 3 to p8 5 and p8 7 as i/o pins (cts i /rts i , clk i , txd i ) of uarti, these pins are forcibly set as i/o pins of uarti regardless of port p8 direction registers contents. figure 7.2.13 shows the relationship between the port p8 direction register and uartis i/o pins. fig. 7.2.13 relationship between port p8 direction register and uartis i/o pins bit corresponding pin functions 0 1 2 3 4 5 6 7 cts 0 / rts 0 pin rxd 0 pin txd 0 pin cts 1 / rts 1 pin rxd 1 pin 0 : input mode 1 : output mode when using pins p8 2 and p8 6 as serial data input pins (rxd 0 , rxd 1 ), set the corresponding bits to 0. clk 1 pin port p8 direction register (address 14 16 ) b1 b0 b2 b3 b4 b5 b6 b7 clk 0 pin txd 1 pin at reset rw 0 0 0 0 0 0 0 0 rw rw rw rw rw rw rw rw
serial i/o 7751 group users manual 7C17 7.3 clock synchronous serial i/o mode 7.3 clock synchronous serial i/o mode table 7.3.1 lists the performance overview in the clock synchronous serial i/o mode, and table 7.3.2 lists the functions of i/o pins in this mode. table 7.3.1 performance overview in clock synchronous serial i/o mode item transfer data format transfer rate transmit/receive control when selecting internal clock when selecting external clock functions transfer data has a length of 8 bits. lsb first or msb first can be selected by software. clock which is brgi outputs divided by 2. maximum 5 mbps ____ ____ cts function or rts function can be selected by software. table 7.3.2 functions of i/o pins in clock synchronous serial i/o mode functions serial data output serial data input transfer clock output transfer clock input ____ cts input ____ rts output pin name txd i (p8 3 , p8 7 ) rxd i (p8 2 , p8 6 ) clk i (p8 1 , p8 5 ) cts i /rts i (p8 0 , p8 4 ) method of selection fixed (dummy data is output when performing only reception.) port p8 direction register \ 1 s corresponding bit = 0 internal/external clock select bit \ 2 = 0 internal/external clock select bit = 1 ____ ____ cts/rts select bit \ 3 = 0 ____ ____ cts/rts select bit = 1 port p8 direction register \ 1 : address 14 16 internal/external clock select bit \ 2 : bit 3 at addresses 30 16 , 38 16 ____ ____ cts/rts select bit \ 3 : bit 2 at addresses 34 16 , 3c 16 notes 1: the txd i pin outputs h level until transmission starts after uartis operating mode is selected. 2: the rxd i pin can be used as a programmable i/o port when performing only transmission.
serial i/o 7751 group users manual 7C18 7.3 clock synchronous serial i/o mode 7.3.1 transfer clock (synchronizing clock) data transfer is performed synchronously with the transfer clock. for the transfer clock, the user can select whether to generate the transfer clock internally or to input it from an external. the transfer clock is generated by operation of the transmit control circuit. accordingly, even when performing only reception, set the transmit enable bit to 1, and set dummy data in the uarti transmit buffer register in order to make the transmit control circuit active. (1) generating transfer clock internally the count source selected with the brg count source select bits is divided by the brgi, and its brgi output is further divided by 2. this is the transfer clock. the transfer clock is output from the clk i pin. [setting relevant registers] ?select an internal clock (bit 3 at addresses 30 16 , 38 16 = 0). ?select the brgis count source (bits 0 and 1 at addresses 34 16 , 3c 16 ) ?set divide value C 1 (= n; 00 16 to ff 16 ) to the brgi (addresses 31 16 , 39 16 ). transfer clock frequency = ?enable transmission (bit 0 at addresses 35 16 , 3d 16 = 1). ?set data to the uarti transmit buffer register (addresses 32 16 , 3a 16 ) [pins state] ?a transfer clock is output from the clk i pin. ?serial data is output from the txdi pin. (dummy data is output when performing only reception.) (2) inputting transfer clock from an external a clock input from the clk i pin is the transfer clock. [setting relevant registers] ?select an external clock (bit 3 at addresses 30 16 , 38 16 = 1). ?enable transmission (bit 0 at addresses 35 16 , 3d 16 = 1). ?set data to the uarti transmit buffer register (addresses 32 16 , 3a 16 ). [pins state] ?a transfer clock is input from the clk i pin. ?serial data is output from the txd i pin. (dummy data is output when performing only reception.) f i 2 (n+1) f i : frequency of brgis count source (f 2/ f 4 , f 16/ f 32 , f 64/ f 128 , f 512/ f 1024 )
serial i/o 7751 group users manual 7C19 7.3 clock synchronous serial i/o mode 7.3.2 transfer data format lsb first or msb first can be selected as the transfer data format. table 7.3.3 lists the relationship between the transfer data format and writing/reading to and from the uarti transmit/receive buffer register. the transfer format select bit (bit 7 at addresses 34 16 , 3c 16 ) selects the transfer data format. when this bit is cleared to 0, the set data is written to the uarti transmit buffer register as the transmit data as it is. similarly, the data in the uarti receive buffer register is read out as the receive data as it is. (refer to the upper row in table 7.3.3.) when this bit is set to 1, each bits position of set data is reversed, and the resultant data is written to the uarti transmit buffer register as the transmit data. similarly, each bits position of data in the uarti receive buffer register is reversed, and the resultant data is read out as the receive data. (refer to the lower row in table 7.3.3.) note that only the method of writing/reading to and from the uarti transmit/receive buffer register is affected by selection of the transfer data format, and that the transmit/receive operation is unaffected by it. table 7.3.3 relationship between transfer data format and writing/reading to and from uarti transmit/ receive buffer register writing to uarti transmit buffer register reading from uarti receive buffer register data bus uarti transmit buffer register db7 db6 db5 db4 db3 db2 db1 db0 data bus uarti receive buffer register db7 db6 db5 db4 db3 db2 db1 db0 lsb (least significant bit) first data bus uarti transmit buffer register d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 data bus uarti receive buffer register msb (most significant bit) first transfer data format transfer format select bit 0 1 db7 db6 db5 db4 db3 db2 db1 db0 db7 db6 db5 db4 db3 db2 db1 db0 d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0
serial i/o 7751 group users manual 7C20 7.3 clock synchronous serial i/o mode 7.3.3 method of transmission figures 7.3.1 shows an initial setting example for relevant registers when transmitting. transmission is started when all of the following conditions ( to a ) are satisfied. when an external clock is selected, satisfy conditions to a with the following precondition satisfied. the clk i pins input is h level note: when an internal clock is selected, above precondition is ignored. transmission is enabled (transmit enable bit = 1). transmit data is present in the uarti transmit buffer register (transmit buffer empty flag = 0) _____ ____ a cts i pins input is l level (when cts function selected). ____ note : when the cts function is not selected, this condition is ignored. when using interrupts, it is necessary to set the relevant register to enable interrupts. for details, refer to chapter 4. interrupts. figure 7.3.2 shows writing data after start of transmission, and figure 7.3.3 shows detection of transmissions completion.
serial i/o 7751 group users manual 7C21 7.3 clock synchronous serial i/o mode fig. 7.3.1 initial setting example for relevant registers when transmitting uart0 transmit buffer register (address 32 16 ) uart1 transmit buffer register (address 3a 16 ) b7 b0 set transmit data here. 1 uart0 transmit/receive control register 1 (address 35 16 ) uart1 transmit/receive control register 1 (address 3d 16 ) b7 b0 transmit enable bit 1: transmission enabled (in the case of selecting the cts function, transmission starts when the cts i pins input level is l.) uart0 transmit/receive control register 0 (address 34 16 ) uart1 transmit/receive control register 0 (address 3c 16 ) b7 b0 brg count source select bits 0 0 : f 2 /f 4 0 1 : f 16 /f 32 1 0 : f 64 /f 128 1 1 : f 512 /f 1024 b1 b0 1 0 0 0 uart0 transmit/receive mode register (address 30 16 ) uart1 transmit/receive mode register (address 38 16 ) b7 b0 internal/external clock select bit 0: internal clock 1: external clock 5 : it may be either 0 or 1. clock synchronous serial i/o mode 555 uart0 transmit interrupt control register (address 71 16 ) uart1 transmit interrupt control register (address 73 16 ) b7 b0 interrupt priority level select bits when using interrupts, set these bits to level 1 - 7. when disabling interrupts, set these bits to level 0. uart0 baud rate register (brg0) (address 31 16 ) uart1 baud rate register (brg1) (address 39 16 ) b7 b0 set to 00 16 to ff 16 . ] necessary only when internal clock is selected. transmission starts. cts / rts select bit 0: cts function selected. 1: rts function selected ( cts function disabled). transfer format select bit 0: lsb first 1: msb first
serial i/o 7751 group users manual 7C22 7.3 clock synchronous serial i/o mode fig. 7.3.2 writing data after start of transmission [when not using interrupts] [when using interrupts] the uarti transmit interrupt request occurs when the uarti transmit buffer register becomes empty. uarti transmit interrupt note : uart0 transmit buffer register (address 32 16 ) uart1 transmit buffer register (address 3a 16 ) b7 b0 writing of next transmit data set transmit data here. b0 uart0 transmit/receive control register 1 (address 35 ) uart1 transmit/receive control register 1 (address 3d ) b7 transmit buffer empty flag 0: data present in transmit buffer register 1: no data present in transmit buffer register (writing of next transmit data is possible.) checking state of uarti transmit buffer register 1 this figure shows the bits and registers required for processing. refer to figure 7.3.5 about the change of flag state and the occurrence timing of an interrupt request. 16 16 b0
serial i/o 7751 group users manual 7C23 7.3 clock synchronous serial i/o mode fig. 7.3.3 detection of transmissions completion [when not using interrupts] [when using interrupts] uarti transmit interrupt uart0 transmit interrupt control register (address 71 16 ) uart1 transmit interrupt control register (address 73 16 ) b7 b0 interrupt request bit checking start of transmission uart0 transmit/receive control register 0 (address 34 16 ) uart1 transmit/receive control register 0 (address 3c 16 ) b7 b0 checking completion of transmission transmit register empty flag 0: during transmitting 1: transmitting completed processing at completion of transmission 0: no interrupt request 1: interrupt request (transmission has started.) the uarti transmit interrupt request occurs when the transmission starts. note : this figure shows the bits and registers required for processing. refer to figure 7.3.5 about the change of flag state and the occurrence timing of an interrupt request.
serial i/o 7751 group users manual 7C24 7.3 clock synchronous serial i/o mode 7.3.4 transmit operation when the transmit conditions described in page 7-20 are satisfied, the following operations are automatically performed simultaneously. ?the uarti transmit buffer registers contents are transferred to the uarti transmit register. ?8 transfer clocks are generated (when an internal clock is selected). ?the transmit buffer empty flag is set to 1. ?the transmit register empty flag is cleared to 0. ?the uarti transmit interrupt request occurs, and the interrupt request bit is set to 1. the transmit operations are described below. data in the uarti transmit register is transmitted from the txd i pin synchronously with the falling of the transfer clock. this data is transmitted bit by bit sequentially beginning with the least significant bit. a when 1-byte data has been transmitted, the transmit register empty flag is set to 1, indicating completion of the transmission. figure 7.3.4 shows the transmit operation. in the case of an internal clock is selected, when the transmit conditions for the next data are satisfied at completion of the transmission, the transfer clock is generated continuously. accordingly, when performing transmission continuously, set the next transmit data to the uarti transmit buffer register during transmission (when the transmit register empty flag = 0). when the transmit conditions for the next data are not satisfied, the transfer clock stops at h level. figures 7.3.5 shows an example of transmit timing (when selecting an internal clock).
serial i/o 7751 group users manual 7C25 7.3 clock synchronous serial i/o mode fig. 7.3.4 transmit operation transfer clock uarti transmit buffer register c d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 7 d 6 d 5 d 4 d 3 d 2 d 7 d 6 d 5 d 4 d 3 transmit data c msb b7 b0 d 0 d 1 d 2 d 7 lsb uarti transmit register d 0 d 1 d 2 d 3 d 4 d 5 d 6 d 7 d 0 d 1 d 2 d 3 d 4 d 5 d 6 d 7 d 0 d 1 d 2 d 3 d 4 d 5 d 6 d 7 tc t clk cts i clk i t end i txd i h l 0 1 0 1 0 1 0 1 transfer clock transmit enable bit transmit buffer empty flag transmit register empty flag uarti transmit interrupt request bit data is set in uarti transmit buffer register. uarti transmit register uarti transmit buffer register. stopped because ctsi = h. stopped because transmit enable bit = 0. t endi : next transmit conditions are examined when this signal level is h. (t endi is an internal signal. accordingly, it cannot be read from an external.) tc = t clk = 2(n+1) /fi fi: brgi count source frequency (f 2 /f 4 , f 16 /f 32 , f 64 /f 128 , f 512 /f 1024 ) n: value set to brgi cleared to 0 when interrupt request is accepted or cleared by software. the above timing diagram applies to the following conditions: l internal clock selected l cts function selected. fig. 7.3.5 example of transmit timing (when selecting internal clock) ? ? ? ? ? ?
serial i/o 7751 group users manual 7C26 7.3 clock synchronous serial i/o mode 7.3.5 method of reception figures 7.3.6 and 7.3.7 show initial setting examples for relevant registers when receiving. reception is started when all of the following conditions ( to a ) are satisfied. when an external clock is selected, satisfy conditions to a with the following precondition satisfied. the clk i pins input is h level. note: when an internal clock is selected, above precondition is ignored. reception is enabled (receive enable bit = 1). transmission is enabled (transmit enable bit = 1). a dummy data is present in the uarti transmit buffer register (transmit buffer empty flag = 0) when using interrupts, it is necessary to set the relevant register to enable interrupts. for details, refer to chapter 4. interrupts. figure 7.3.8 shows processing after receptions completion.
serial i/o 7751 group users manual 7C27 7.3 clock synchronous serial i/o mode fig. 7.3.6 initial setting example for relevant registers when receiving (1) ] necessary only when an internal clock is selected. uart0 baud rate register (brg0) (address 31 16 ) uart1 baud rate register (brg1) (address 39 16 ) b7 b0 set to 00 16 to ff 16 . 1 0 0 0 uart0 transmit/receive mode register (address 30 16 ) uart1 transmit/receive mode register (address 38 16 ) b7 b0 internal/external clock select bit 0: internal clock 1: external clock 5 : it may be either 0 or 1. clock synchronous serial i/o mode continued to figure 7.3.7 on next page. uart0 transmit/receive control register 0 (address 34 16 ) uart1 transmit/receive control register 0 (address 3c 16 ) b7 b0 cts / rts select bit 0: cts function selected ( rts function disabled). 1: rts function selected. 555 brg count source select bits b1 b0 0 0 : f 2 /f 4 0 1 : f 16 /f 32 1 0 : f 64 /f 128 1 1 : f 512 /f 1024 transfer format select bit 0: lsb first 1: msb first
serial i/o 7751 group users manual 7C28 7.3 clock synchronous serial i/o mode fig. 7.3.7 initial setting example for relevant registers when receiving (2) port p8 direction register (address 14 16 ) b7 b0 0 r x d 0 pin 0 r x d 1 pin from preceding figure 7.3.6 uart0 receive interrupt control register (address 72 16 ) uart1 receive interrupt control register (address 74 16 ) b7 b0 interrupt priority level select bits when using interrupts, set these bits to level 1C7. when disabling interrupts, set these bits to level 0. uart0 transmit buffer register (address 32 16 ) uart1 transmit buffer register (address 3a 16 ) b7 b0 set dummy data here. uart0 transmit/receive control register 1 (address 35 16 ) uart1 transmit/receive control register 1 (address 3d 16 ) b7 b0 transmit enable bit 1 : transmission enabled 1 1 receive enable bit 1 : reception enabled reception starts. note: set the receive enable bit and the transmit enable bit to 1 simultaneously.
serial i/o 7751 group users manual 7C29 7.3 clock synchronous serial i/o mode fig. 7.3.8 processing after receptions completion [when not using interrupts] [when using interrupts] the uarti receive interrupt request occurs when reception is completed. uarti receive interrupt processing after reading out receive data uart0 receive buffer register (address 36 16 ) uart1 receive buffer register (address 3e 16 ) b7 b0 reading of receive data read out receive data. b7 b0 checking completion of reception 1 1 note : this figure shows the bits and registers required for processing. refer to figure 7.3.11 about the change of flag state and the occurrence timing of an interrupt request. b7 b0 checking error 1 1 overrun error flag 0: no overrun error 1: overrun error detected uart0 transmit/receive control register 1 (address 35 16 ) uart1 transmit/receive control register 1 (address 3d 16 ) uart0 transmit/receive control register 1 (address 35 16 ) uart1 transmit/receive control register 1 (address 3d 16 ) receive complete flag 0: reception not completed 1: reception completed
serial i/o 7751 group users manual 7C30 7.3 clock synchronous serial i/o mode 7.3.6 receive operation when the receive conditions listed on page 7-26 are satisfied, the uarti enters the receive enable state. the receive operations are described below. the input signal of the rxd i pin is taken into the most significant bit of the uarti receive register synchronously with the rising of the transfer clock. the contents of the uarti receive register are shifted by 1 bit to the right. a steps and are repeated at each rising of the transfer clock. ? when 1-byte data is prepared in the uarti receive register, the contents of this register are transferred to the uarti receive buffer register. ? simultaneously with step ? , the receive complete flag is set to 1, and the uarti receive interrupt request occurs and its interrupt request bit is set to 1. the receive complete flag is cleared to 0 when the low-order byte of the uarti receive buffer register is read out. figure 7.3.10 shows the receive operation, and figure 7.3.11 shows an example of receive timing (when selecting an external clock). when the transfer format select bit = 1 (msb first), each bits position of this registers contents is reversed and the resultant data is read out. fig. 7.3.9 connection example txd i rxd i clk i txd i rxd i clk i transmitter side receiver side
serial i/o 7751 group users manual 7C31 7.3 clock synchronous serial i/o mode fig. 7.3.10 receive operation uarti receive register d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 d 0 d 1 d 0 receive data msb b7 b0 lsb d 2 d 1 d 0 transfer clock uarti receive buffer register ? ? ? ? ? ?
serial i/o 7751 group users manual 7C32 7.3 clock synchronous serial i/o mode d 0 d 1 d 2 d 3 d 4 d 5 d 6 d 7 d 0 d 1 d 2 d 3 d 4 d 5 1/f ext rts i clk i rxd i h l 0 1 0 1 0 1 0 1 0 1 : when the clki pins input level is h, satisfy the following cinditions: l transmit enable bit ? 1 l receive enable bit ? 1 l writing of dummy data to uarti transmit buffer register receive enable bit transmit enable bit transmit buffer empty flag dummy data is set to uarti transmit buffer register. uarti transmit register ? uarti transmit buffer register received data taken in uarti receive register ? uarti receive buffer register uarti receive buffer register is read out. receive complete flag uarti receive interrupt request bit the above timing diagram applies to the following setting conditions: cleared to 0 when interrupt request is accepted or cleared by software. l external clock selected. l rts function selected. f ext : frequency of external clock fig. 7.3.11 example of receive timing (when selecting external clock)
serial i/o 7751 group users manual 7C33 7.3 clock synchronous serial i/o mode 7.3.7 process on detecting overrun error in the clock synchronous serial i/o mode, an overrun error can be detected. an overrun error occurs when the next data is prepared in the uarti receive register with the receive complete flag = 1 (data is present in the uarti receive buffer register) and that is transferred to the receive buffer register, in other words, when the next data is prepared before reading out the contents of the uarti receive buffer register. when an overrun error occurs, the next receive data is written into the uarti receive buffer register, and the uarti receive interrupt request bit is not changed. an overrun error is detected when data is transferred from the uarti receive register to the uarti receive buffer register and the overrun error flag is set to 1. the overrun error flag is cleared to 0 by clearing the receive enable bit to 0. when an overrun error occurs during reception, initialize the overrun error flag and the uarti receive buffer register before performing reception again. when it is necessary to perform retransmission owing to an overrun error which occurs in the receiver side, set the uarti transmit buffer register again before starting transmission again. the method of initializing the uarti receive buffer register and that of setting the uarti transmit buffer register again are described below. (1) method of initializing uarti receive buffer register clear the receive enable bit to 0 (reception disabled). set the receive enable bit to 1 again (reception enabled). (2) method of setting uarti transmit buffer register again clear the serial i/o mode select bits to 000 2 (serial i/o ignored). set the serial i/o mode select bits to 001 2 again. a set the transmit enable bit to 1 (transmission enabled), and set the transmit data to the uarti transmit buffer register.
serial i/o 7751 group users manual 7C34 7.3 clock synchronous serial i/o mode [precautions when operating in clock synchronous serial i/o mode] 1. the transfer clock is generated by operation of the transmit control circuit. accordingly, even when performing only reception, transmit operation (setting for transmission) must be performed. in this case, dummy data is output from the txd i pin. 2. when receiving, simultaneously set the receive enable bit and the transmit enable bit to 1. 3. when selecting an external clock, satisfy the following 3 conditions with the input to clk i pin = h level. set the transmit enable bit to 1. write transmit data to the uarti transmit buffer register. ____ ____ a input l level to the cts i pin (when selecting the cts function). set the receive enable bit to 1. set the transmit enable bit to 1. a write dummy data to the uarti transmit buffer register. 4. when receiving data, write dummy data to the low-order byte of the uarti transmission buffer register for each reception of 1-byte data. ____ 5. the output level of the rts i pin becomes l simultaneously at setting the receive enable bit to 1. the output level of this pin becomes h when receive starts, and it becomes l when receive is completed. the output level of this pin changes regardless of the contents of the transmit enable bit, the transmission buffer empty flag, and the receive complete flag.
7751 group users manual 7C35 serial i/o 7.4 clock asynchronous serial i/o (uart) mode 7.4 clock asynchronous serial i/o (uart) mode table 7.4.1 lists the performance overview in the uart mode, and table 7.4.2 lists the functions of i/o pins in this mode. table 7.4.1 performance overview in uart mode item transfer data format transfer rate error detection start bit character bit (transfer data) parity bit stop bit when selecting internal clock when selecting external clock functions 1 bit 7 bits, 8 bits, or 9 bits 0 bit or 1 bit (odd or even can be selected.) 1 bit or 2 bits clock of brgi output divided by 16 maximum 312.5 kbps 4 types (overrun, framing, parity, and summing) presence of error can be detected only by checking error sum flag. table 7.4.2 functions of i/o pins in uart mode method of selection fixed port p8 direction register \ 1 s corresponding bit = 0 internal/external clock select bit \ 2 = 1 ____ ____ cts/rts select bit \ 3 = 0 ____ ____ cts/rts select bit = 1 pin name txd i (p8 3 , p8 7 ) rxd i (p8 2 , p8 6 ) clk i (p8 1 , p8 5 ) ____ ____ cts i / rts i (p8 0 , p8 4 ) functions serial data output serial data input brgis count source input ____ cts input ____ rts output port p8 direction register \ 1 : address 14 16 internal/external clock select bit \ 2 : bit 3 at addresses 30 16 , 38 16 ____ ____ cts/rts select bit \ 3 : bit 2 at addresses 34 16 , 3c 16 notes 1 : the txd i pin outputs h level while not transmitting after selecting uartis operating mode. 2 : the rxd i pin can be used as a programmable i/o port when performing only transmission. 3 : the clk i pin can be used as a programmable i/o port when selecting internal clock. ___ ___ ___ 4: the cts i /rts i pin can be used as a input port when performing only reception and not using rts ___ function (when selecting cts function).
serial i/o 7751 group users manual 7C36 7.4 clock asynchronous serial i/o (uart) mode 7.4.1 transfer rate (frequency of transfer clock) the transfer rate is determined by the brgi (addresses 31 16 , 39 16 ). when setting n into brgi (n = 00 16 to ff 16 ), brgi divides the count source frequency by n + 1. the divided clock by brgi is further divided by 16 and the resultant clock becomes the transfer clock. accordingly, the value n is expressed by the following formula. n = 1 f 16 5 b n: value set into brgi (00 16 to ff 16 ) f: brgis count source frequency b: transfer rate (bps) an internal clock or an external clock can be selected as the brgis count source with the internal/external clock select bit (bit 3 at addresses 30 16 , 38 16 ). when an internal clock is selected, the clock selected with the brg count source select bits (bits 0 and 1 at addresses 34 16 , 3c 16 ) becomes the brgis count source. when an external clock is selected, the clock input to the clk i pin becomes the brgis count source. tables 7.4.3 to 7.4.5 are list the setting examples of transfer rate. set the same transfer rate between the transmitter and the receiver. table 7.4.3 setting examples of transfer rate (1) transfer rate (bps) 150 300 600 1200 2400 4800 9600 19200 31250 brgi setting value : n 162 (a2 16 ) 80 (50 16 ) 162 (a2 16 ) 80 (50 16 ) 40 (28 16 ) 162 (a2 16 ) 80 (50 16 ) 40 (28 16 ) 24 (18 16 ) actual time (bps) 149.78 301.41 599.12 1205.63 2381.86 4792.94 9645.06 19054.88 31250.00 brgi count source f 128 f 32 f 32 f 32 f 4 f 4 f 4 brgi setting value : n 80 (50 16 ) 162 (a2 16 ) 80 (50 16 ) 40 (28 16 ) 162 (a2 16 ) 80 (50 16 ) 40 (28 16 ) actual time (bps) 150.70 299.56 602.82 1190.93 2396.47 4822.53 9527.44 brgi count source f 64 f 64 f 16 f 16 f 16 f 2 f 2 f 2 f 2 clock source for peripheral devices select bit = 0 f(x in ) = 25 mhz clock source for peripheral devices select bit = 1 clock source for peripheral devices select bit : bit 2 at address 5f 16
7751 group users manual 7C37 serial i/o 7.4 clock asynchronous serial i/o (uart) mode table 7.4.4 setting examples of transfer rate (2) transfer rate (bps) 150 300 600 1200 2400 4800 9600 19200 31250 brgi setting value : n 159 (9f 16 ) 79 (4f 16 ) 159 (9f 16 ) 79 (4f 16 ) 39 (27 16 ) 159 (9f 16 ) 79 (4f 16 ) 39 (27 16 ) actual time (bps) 150.00 300.00 600.00 1200.00 2400.00 4800.00 9600.00 19200.00 brgi count source f 128 f 32 f 32 f 32 f 4 f 4 f 4 f 4 brgi setting value : n 79 (4f 16 ) 159 (9f 16 ) 79 (4f 16 ) 39 (27 16 ) 159 (9f 16 ) 79 (4f 16 ) 39 (27 16 ) 19 (13 16 ) actual time (bps) 150.00 300.00 600.00 1200.00 2400.00 4800.00 9600.00 19200.00 brgi count source f 64 f 64 f 16 f 16 f 16 f 2 f 2 f 2 clock source for peripheral devices select bit = 1 clock source for peripheral devices select bit = 0 f(x in ) = 24.576 mhz clock source for peripheral devices select bit : bit 2 at address 5f 16 table 7.4.5 setting examples of transfer rate (3) transfer rate (bps) 150 300 600 1200 2400 4800 9600 19200 31250 brgi setting value : n 127 (7f 16 ) 255 (ff 16 ) 127 (7f 16 ) 63 (3f 16 ) 255 (ff 16 ) 127 (7f 16 ) 63 (3f 16 ) 31 (1f 16 ) actual time (bps) 150.00 300.00 600.00 1200.00 2400.00 4800.00 9600.00 19200.00 brgi count source f 128 f 128 f 32 f 32 f 32 f 4 f 4 f 4 f 4 brgi setting value : n 129 (81 16 ) 64 (40 16 ) 129 (81 16 ) 64 (40 16 ) 32 (20 16 ) 129 (81 16 ) 64 (40 16 ) 32 (20 16 ) 19 (13 16 ) actual time (bps) 150.24 300.48 600.96 1201.92 2367.42 4807.69 9615.38 18939.39 31250.00 brgi count source f 128 f 32 f 32 f 32 f 4 f 4 f 4 f 4 f(x in ) = 39.3216 mhz f(x in ) = 40 mhz clock source for peripheral devices select bit : bit 2 at address 5f 16 clock source for peripheral devices select bit = 0
serial i/o 7751 group users manual 7C38 7.4 clock asynchronous serial i/o (uart) mode 7.4.2 transfer data format the transfer data format can be selected from formats shown in figure 7.4.1. bits 4 to 6 at addresses 30 16 and 38 16 select the transfer data format. (refer to figure 7.1.1.) set the same transfer data format for both transmitter and receiver sides. figure 7.4.2 shows an example of transfer data format. table 7.4.6 lists each bit in transmit data. transfer data length of 7 bits 1st7data 1sp 1st7data 2sp 1st7data1par1sp 1st7data1par2sp transfer data length of 8 bits 1st8data 1sp 1st8data 2sp 1st8data1par1sp 1st8data1par2sp transfer data length of 9 bits 1st9data 1sp 1st9data 2sp 1st9data1par1sp 1st9data1par2sp st : start bit data : character bit (transfer data) par : parity bit sp : stop bit fig. 7.4.1 transfer data format
7751 group users manual 7C39 serial i/o 7.4 clock asynchronous serial i/o (uart) mode name st start bit data character bit par parity bit st stop bit functions l signal equivalent to 1 character bit which is added immediately before the character bits. it indicates start of data transmission. transmit data which is set in the uarti transmit buffer register. a signal that is added immediately after the character bits in order to improve data reliability. the level of this signal changes according to selection of odd/even parity in such a way that the sum of 1s in this bit and character bits is always an odd or even number. h level signal equivalent to 1 or 2 character bits which is added immediately after the character bits (or parity bit when parity is enabled). it indicates finish of data transmission. fig. 7.4.2 example of transfer data format table 7.4.6 each bit in transmit data time ?example of 1stC8dataC1parC1sp st lsb msb par sp st transmit/receive data h data (8 bits) next transmit/receive data (when continuously transferring)
serial i/o 7751 group users manual 7C40 7.4 clock asynchronous serial i/o (uart) mode 7.4.3 method of transmission figure 7.4.3 shows an initial setting example for relevant registers when transmitting. the difference due to selection of transfer data length (7 bits, 8 bits, or 9 bits) is only that data length. when selecting a 7- or 8-bit data length, set the transmit data into the low-order byte of the uarti transmit buffer register. when selecting a 9-bit data length, set the transmit data into that low-order byte and bit 0 of that high-order byte. transmission is started when all of the following conditions ( to a ) are satisfied: transmit is enabled (transmit enable bit = 1). transmit data is present in the uarti transmit buffer register (transmit buffer empty flag = 0). ____ ____ a cts i pins input is l level (when cts function selected). ____ note: when the cts function is not selected, this condition is ignored. when using interrupts, it is necessary to set the corresponding register to enable interrupts. for details, refer to chapter 4. interrupts. figure 7.4.4 shows writing data after start of transmission, and figure 7.4.5 shows detection of transmissions completion.
7751 group users manual 7C41 serial i/o 7.4 clock asynchronous serial i/o (uart) mode fig. 7.4.3 initial setting example for relevant registers when transmitting uart0 baud rate register (brg0) (address 31 16 ) uart1 baud rate register (brg1) (address 39 16 ) b7 b0 set to 00 16 to ff 16 . interrupt priority level select bits when using interrupts, set these bits to level 1C7. when disabling interrupts, set these bits to level 0. uart0 transmit interrupt control register (address 71 16 ) uart1 transmit interrupt control register (address 73 16 ) b7 1 uart0 transmit/receive control register 1 (address 35 16 ) uart1 transmit/receive control register 1 (address 3d 16 ) b7 b0 transmit enable bit 1: transmission enabled transmission starts. b0 uart0 transmit buffer register (addresses 33 16 , 32 16 ) uart1 transmit buffer register (addresses 3b 16 , 3a 16 ) b7 b0 set transmit data here. uart0 transmit/receive mode register (address 30 16 ) uart1 transmit/receive mode register (address 38 16 ) b7 b0 internal/external clock select bit 0: internal clock 1: external clock 1 0 0: uart mode (7 bits) 1 0 1: uart mode (8 bits) 1 1 0: uart mode (9 bits) stop bit length select bit 0: 1 stop bit 1: 2 stop bits odd/even parity select bit 0: odd parity 1: even parity parity enable bit 0: parity disabled 1: parity enabled sleep select bit 0: sleep mode cleared (ignored) 1: sleep mode selected 1 b2 b1 b0 uart0 transmit/receive control register 0 (address 34 16 ) uart1 transmit/receive control register 0 (address 3c 16 ) b7 b0 brg count source select bits cts / rts select bit 0: cts function selected 1: rts function selected (cts function disabled) 0 0: f 2 /f 4 0 1: f 16 /f 32 1 0: f 64 /f 128 1 1: f 512 /f 1024 b1 b0 (in the case of selecting the cts function, transmission starts when the cts i pins input level is l.) b8 0
serial i/o 7751 group users manual 7C42 7.4 clock asynchronous serial i/o (uart) mode fig. 7.4.4 writing data after start of transmission [when not using interrupts] [when using interrupts] the uarti transmit interrupt request occurs when the uarti transmit buffer register becomes empty. uarti transmit interrupt note : uart0 transmit buffer register (addresses 33 16 , 32 16 ) uart1 transmit buffer register (addresses 3b 16 , 3a 16 ) b7 b0 writing of next transmit data set transmit data here. b0 uart0 transmit/receive control register 1 (address 35 16 ) uart1 transmit/receive control register 1 (address 3d 16 ) b7 transmit buffer empty flag 0: data present in transmit buffer register 1: no data present in transmit buffer register (writing of next transmit data is possible.) checking state of uarti transmit buffer register 1 this figure shows the bits and registers required for processing. refer to figures 7.4.6 and 7.4.7 about the change of flag state and the occurrence timing of an interrupt request. b0 b8 b15
7751 group users manual 7C43 serial i/o 7.4 clock asynchronous serial i/o (uart) mode fig. 7.4.5 detection of transmissions completion [when not using interrupts] [when using interrupts] uarti transmit interrupt uart0 transmit interrupt control register (address 71 16 ) uart1 transmit interrupt control register (address 73 16 ) b7 b0 interrupt request bit checking start of transmission uart0 transmit/receive control register 0 (address 34 16 ) uart1 transmit/receive control register 0 (address 3c 16 ) b7 b0 checking completion of transmission. transmit register empty flag 0: during transmitting 1: transmitting completed processing at completion of transmission 0: 1: no interrupt request interrupt request (transmission has started.) the uarti transmit interrupt request occurs when the transmission starts. note : this figure shows the bits and registers required for processing. refer to figures 7.4.6 to 7.4.7 about the change of flag state and the occurrence timing of an interrupt request. 0
serial i/o 7751 group users manual 7C44 7.4 clock asynchronous serial i/o (uart) mode 7.4.4 transmit operation simultaneously when the transmit conditions listed on page 7-40 are satisfied, the following operations are automatically performed. ?the uarti transmit buffer registers contents are transferred to the uarti transmit register. ?the transmit buffer empty flag is set to 1. ?the transmit register empty flag is cleared to 0. ?the uarti transmit interrupt request occurs and the interrupt request bit is set to 1. the transmit operations are described below. data in the uarti transmit register is transmitted from the txd i pin. this data is transmitted bit by bit sequentially in order of st ? data (lsb) ? ??? ? data (msb) ? par ? sp according to the set transfer data format. a when the stop bit has been transmitted, the transmission register empty flag is set to 1, indicating completion of transmission. when the transmit conditions for the next data are satisfied at completion of transmission, the start bit is generated following the stop bit, and the next data is transmitted. when performing transmission continuously, set the next transmit data in the uarti transmit buffer register during transmission (when the transmit register empty flag = 0). when the transmit conditions for the next data are not satisfied, the txd i pin outputs h level. figures 7.4.6 shows example of transmit timing when the transfer data length is 8 bits, and figure 7.4.7 shows an example of transmit timing when the transfer data length is 9 bits.
7751 group users manual 7C45 serial i/o 7.4 clock asynchronous serial i/o (uart) mode fig. 7.4.6 example of transmit timing when transfer data length is 8 bits (when parity enabled, selecting 1 stop bit) fig. 7.4.7 example of transmit timing when transfer data length is 9 bits (when parity disabled, selecting 2 stop bits) tc d 0 d 1 d 2 d 3 d 4 d 5 d 6 d 7 st p sp d 0 d 1 d 0 d 1 d 2 d 3 d 4 d 5 d 6 d 7 st p sp st t endi txd i cts i 0 1 0 1 l h 0 1 0 1 t endi : next transmit conditions are examined when this signal level is h. (t endi is an internal signal. accordingly, it cannot be read from an external.) tc: 16(n + 1)/fi or 16(n + 1)/f ext fi: brgi count source frequency (f 2 /f 4 , f 16 /f 32 , f 64 /f 128 , f 512 /f 1024 ) f ext : brgi count source frequency (external clock) n: value set to brgi transfer clock transmit enable bit transmit buffer empty flag transmit register empty flag uarti transmit interrupt request bit data is set in uarti transmit buffer register. start bit parity bit cleared to 0 when interrupt request is accepted or cleared by software. the above timing diagram applies to the following conditions: l parity enabled l 1 stop bit l cts function selected uarti transmit register uarti transmit buffer register stopped because transmit enable bit = 0 stop bit d 0 d 1 d 2 d 3 d 4 d 5 d 6 d 7 st d 8 d 0 d 1 d 2 d 3 d 4 d 5 d 6 d 7 st sp d 0 d 1 st d 8 sp sp sp 0 1 0 1 0 1 tc 0 1 t endi txd i t endi : next transmit conditions are examined when this signal level is h. (t endi is an internal signal. accordingly, it cannot be read from an external.) tc: 16(n + 1)/fi or 16(n + 1)/f ext fi: brgi count source frequency (f 2 /f 4 , f 16 /f 32 , f 64 /f 128 , f 512 /f 1024 ) f ext : brgi count source frequency (external clock) n: value set to brgi transfer clock transmit enable bit transmit buffer empty flag transmit register empty flag uarti transmit interrupt request bit data is set in uarti transmit buffer register. start bit cleared to 0 when interrupt request is accepted or cleared by software. the above timing diagram applies to the following conditions: l parity disabled l 2 stop bits l cts function disabled uarti transmit register uarti transmit buffer register stopped because transmit enable bit = 0 stop bit stop bit
serial i/o 7751 group users manual 7C46 7.4 clock asynchronous serial i/o (uart) mode 7.4.5 method of reception figure 7.4.8 shows an initial setting example for relevant registers when receiving. reception is started when all of the following conditions ( and ) are satisfied: reception is enabled (receive enable bit = 1). the start bit is detected. when using interrupts, it is necessary to set the corresponding register to enable interrupts. for details, refer to chapter 4. interrupts. figure 7.4.9 shows processing after receptions completion.
7751 group users manual 7C47 serial i/o 7.4 clock asynchronous serial i/o (uart) mode fig. 7.4.8 initial setting example for relevant registers when receiving reception starts when the start bit is detected. port p8 direction register (address 14 16 ) b7 b0 0 0 rxd 0 pin rxd 1 pin uart0 baud rate register (brg0) (address 31 16 ) uart1 baud rate register (brg1) (address 39 16 ) b7 b0 set to 00 16 to ff 16 . uart0 receive interrupt control register (address 72 16 ) uart1 receive interrupt control register (address 74 16 ) b7 b0 interrupt priority level select bits when using interrupts, set these bits to level 1C7. when disabling interrupts, set these bits to level 0. note : set the transfer data format in the same way as set on the transmitter side. 1 uart0 transmit/receive control register 1 (address 35 16 ) uart1 transmit/receive control register 1 (address 3d 16 ) b7 b0 receive enable bit 1: reception enabled uart0 transmit/receive mode register (address 30 16 ) uart1 transmit/receive mode register (address 38 16 ) b7 b0 internal/external clock select bit 0: internal clock 1: external clock 1 0 0: uart mode (7 bits) 1 0 1: uart mode (8 bits) 1 1 0: uart mode (9 bits) stop bit length select bit 0: 1 stop bit 1: 2 stop bits odd/even parity select bit 0: odd parity 1: even parity parity enable bit 0: parity disabled 1: parity enabled sleep select bit 0: sleep mode cleared (ignored) 1: sleep mode selected 1 b2 b1 b0 uart0 transmit/receive control register 0 (address 34 ) uart1 transmit/receive control register 0 (address 3c ) b7 b0 brg count source select bits cts / rts select bit 0 : cts function selected ( rts function disabled) 1 : rts function selected 0 0 : f 2 /f 4 0 1 : f 16 /f 32 1 0 : f 64 /f 128 1 1 : f 512 /f 1024 b1b0 16 16 0
serial i/o 7751 group users manual 7C48 7.4 clock asynchronous serial i/o (uart) mode fig. 7.4.9 processing after receptions completion [when not using interrupts] [when using interrupts] the uarti receive interrupt request occurs when reception is completed. uarti receive interrupt processing after reading out receive data uart0 receive buffer register (addresses 37 16 , 36 16 ) uart1 receive buffer register (addresses 3f 16 , 3e 16 ) b15 b8 reading of receive data read out receive data. b7 b0 0 0 0 0 0 0 0 uart0 transmit/receive control register 1 (address 35 16 ) uart1 transmit/receive control register 1 (address 3d 16 ) b7 b0 receive complete flag 0 : reception not completed 1 : reception completed checking completion of reception 1 uart0 transmit/receive control register 1 (address 35 16 ) uart1 transmit/receive control register 1 (address 3d 16 ) b7 b0 checking error framing error flag parity error flag error sum flag 0 : no error 1 : error detected 1 note : this figure shows the bits and registers required for processing. refer to figure 7.4.11 about the change of flag state and the occurrence timing of an interrupt request. uart0 transmit/receive control register 1 (address 35 16 ) uart1 transmit/receive control register 1 (address 3d 16 ) b7 b0 checking error overrun error flag 0 : no overrun error 1 : overrun error detected 1
7751 group users manual 7C49 serial i/o 7.4 clock asynchronous serial i/o (uart) mode 7.4.6 receive operation when the receive enable bit is set to 1, the uarti enters the reception enabled state and reception starts at detecting st. the receive operation is described below. the input signal of the rxd i pin is taken into the most significant bit of the uarti receive register synchronously with the transfer clocks rising. the contents of uarti receive register are shifted by 1 bit to the right. a steps and are repeated at each rising of the transfer clock. ? when one set of data has been prepared, in other words, the shift according to the selected data format has been completed; the uarti receive registers contents are transferred to the uarti receive buffer register. ? simultaneously with step ? , the receive complete flag is set to 1, and the uarti receive interrupt request occurs and its interrupt request bit is set to 1. the receive complete flag is cleared to 0 when the low-order byte of the uarti receive buffer register is read out. figure 7.4.11 shows an example of receive timing when the transfer data length is 8 bits. fig. 7.4.10 connection example txd i rxd i txd i rxd i transmitter side receiver side
serial i/o 7751 group users manual 7C50 7.4 clock asynchronous serial i/o (uart) mode fig. 7.4.11 example of receive timing when transfer data length is 8 bits (when parity disabled, selecting 1 stop bit) d 0 d 1 d 7 rxd i rts i 1 0 0 1 h l 0 1 the above timinig diagram applies to the following conditions: l parity disabled l 1 stop bit l rts function selected brgi count source receive enable bit transfer clock receive complete flag uarti receive interrupt request bit start bit sampled l receive data taken in stop bit reception started at falling of start bit uarti receive register uarti receive buffer register cleared to 0 when interrupt request is accepted or cleared by software.
7751 group users manual 7C51 serial i/o 7.4 clock asynchronous serial i/o (uart) mode 7.4.7 process on detecting error errors listed below can be detected in the uart mode: l overrun error an overrun error occurs when the next data is prepared in the uarti receive register with the receive completion flag = 1 (that is, data present in the uarti receive buffer register) and that data is transferred to the uarti receive buffer register. in other words, when the next data is prepared before the contents of the uarti receive buffer register is read out, an overrun error occurs. when an overrun error occurs, the next receive data is written into the uarti receive buffer register, and the uarti receive interrupt request bit is not changed. l framing error a framing error occurs when the number of detected stop bits does not match the number of stop bits set. (the uarti interrupt request bit becomes 1.) l parity error a parity error occurs when the sum of 1s in the parity bit and character bits does not match the number of 1s set. (the uarti interrupt request bit becomes 1.) each error is detected when data is transferred from the uarti receive register to the uarti receive buffer register, and the corresponding error flag is set to 1. furthermore, when any of the above errors occurs, the error sum flag is set to 1. accordingly, the error sum flag informs the user whether any error has occurred or not. the overrun error flag is cleared to 0 by clearing the receive enable bit to 0. the framing error flag and the parity error flag are cleared to 0 by reading the contents of the uarti receive buffer register low-order byte or clearing the receive enable bit to 0. the error sum flag is cleared to 0 by clearing the all error flags, which are overrun, framing, and parity. when errors occur during reception, initialize the error flags and the uarti receive buffer register, and then perform reception again. when it is necessary to perform retransmission owing to an error which occurs in the receiver side, set the uarti transmit buffer register again, and then starts transmission again. the method of initializing the uarti receive buffer register and that of setting the uarti transmit buffer register again are described below. (1) method of initializing uarti receive buffer register clear the receive enable bit to 0 (reception disabled). set the receive enable bit to 1 again (reception enabled). (2) method of setting uarti transmit buffer register again clear the serial i/o mode select bits to 000 2 (serial i/o ignored). set the serial i/o mode select bits again. a set the transmit enable bit to 1 (transmission enabled), and set the transmit data to the uarti transmit buffer register.
serial i/o 7751 group users manual 7C52 7.4 clock asynchronous serial i/o (uart) mode 7.4.8 sleep mode this mode is used to transfer data between the specified microcomputers, which are connected by using uarti. the sleep mode is selected by setting the sleep select bit (bit 7 at addresses 30 16 , 38 16 ) to 1 when receiving. in the sleep mode, receive operation is performed when the msb (d 8 when the transfer data length is 9 bits, d 7 when it is 8 bits, d 6 when it is 7 bits) of the receive data is 1. receive operation is not performed when the msb is 0. (the uarti receive registers contents are not transferred to the uarti receive buffer register. additionally, the receive complete flag and error flags do not change and the uarti receive interrupt request does not occur.) the following shows an usage example of sleep mode when the transfer data length is 8 bits. set the same transfer data format for the master and slave microcomputers. select the sleep mode for the slave microcomputers. transmit data, which has 1 in bit 7 and the address of the slave microcomputer with which communicates in bits 0 to 6, from the master microcomputer to all slave microcomputers. a all slave microcomputers receive data of step . (at this time, the uarti receive interrupt request occurs.) ? in all slave microcomputers, check in the interrupt routine whether bits 0 to 6 in the receive data match their addresses. ? in the slave microcomputer of which address matches bits 0 to 6 in the receive data, clear the sleep mode. (do not clear the sleep mode for the other slave microcomputers.) by performing steps to ? , specification of the microcomputer performing transfer is realized. ? transmit data, which has 0 in bit 7, from the master microcomputer. (only the microcomputer specified in steps to ? can receive this data. the other microcomputers do not receive this data.) ? by repeating step ? , transfer can be performed between the same microcomputers continuously. when communicating with another microcomputer, perform steps to ? in order to specify the new slave microcomputer. fig. 7.4.12 sleep mode master slave b slave a slave d slave c transfer data between the master microcomputer and one slave microcomputer selected from multiple slave microcomputers.
chapter 8 a-d converter 8.1 overview 8.2 block description 8.3 a-d conversion method (succesive approximation conversion method) 8.4 absolute accuracy and differential non-linearity error 8.5 comparison voltage in 8-bit mode 8.6 one-shot mode 8.7 repeat mode 8.8 single sweep mode 8.9 repeat sweep mode 0 8.10 repeat sweep mode 1
a-d converter 7751 group users manual 8C2 8.1 overview the a-d converter has the performance specifications listed in table 8.1.1. table 8.1.1 performance specifications of a-d converter 8.1 overview item a-d conversion method resolution absolute accuracy analog input pin conversion rate per analog input pin performance specifications successive approximation conversion method either 8 bits or 10 bits can be selected by software 8-bit mode: 2 lsb 10-bit mode: 3 lsb 8 pins (an 0 to an 7 ) 8-bit mode: 49 f ad ] cycles 10-bit mode: 59 f ad ] cycles f ad ] : a-d converters operation clock the a-d converter has the 5 operation modes listed below. ?one-shot mode this mode is used to perform the operation once for a voltage input from one selected analog input pin. ?repeat mode this mode is used to perform the operation repeatedly for a voltage input from one selected analog input pin. ?single sweep mode this mode is used to perform the operation for voltages input from multiple selected analog input pins, one at a time. ?repeat sweep mode 0 this mode is used to perform the operation repeatedly for voltages input from multiple selected analog input pins. ?repeat sweep mode 1 this mode is used to perform the operation repeatedly for voltages input from all analog input pins. in this mode, analog input pins are separated into two groups according to the frequency of use. one is the group for more frequencies of use, and the other is the group for fewer frequencies of use.
a-d converter 7751 group users manual 8C3 8.2 block description figure 8.2.1 shows the block diagram of the a-d converter. registers relevant to the a-d converter are described below. 8.2 block description fig. 8.2.1 block diagram of a-d converter av ss v ref v ref an 0 an 1 an 2 an 3 an 4 an 5 an 6 an 7 /ad trg v in 1/2 f 2 /f 4 1/2 ad decoder register ladder network successive approximation register a-d register 2 a-d register 3 a-d register 4 a-d register 5 a-d register 6 a-d register 7 a-d register 0 a-d register 1 a-d control register 0 comparator selector data bus (even) a-d sweep pin select register 1 a-d conversion frequency selected data bus (odd)
a-d converter 7751 group users manual 8C4 8.2.1 a-d control register 0 figure 8.2.2 shows the structure of the a-d control register 0. the a-d operation mode select bits 0 select the operation mode of the a-d converter. the other bits are described below. 8.2 block description fig. 8.2.2 structure of a-d control register 0 (1) analog input select bits (bits 2 to 0) these bits are used to select an analog input pin in the one-shot mode and repeat mode. pins which are not selected as analog input pins function as programmable i/o ports. these bits must be set again when the user switches the a-d operation mode to the one-shot mode or repeat mode after performing the operation in the single sweep mode, repeat sweep mode 0 or repeat sweep mode 1. b7 b6 b5 b4 b3 b2 b1 b0 a-d control register 0 (address 1e 16 ) bit a-d conversion frequency ( f ad ) select bit 0 a-d conversion start bit trigger select bit 4 a-d operation mode select bits 0 2 1 0 bit name at reset 0 undefined rw functions 0 0 0 : an 0 selected 0 0 1 : an 1 selected 0 1 0 : an 2 selected 0 1 1 : an 3 selected 1 0 0 : an 4 selected 1 0 1 : an 5 selected 1 1 0 : an 6 selected 1 1 1 : an 7 selected (note 2) b2 b1 b0 0 : internal trigger 1 : external trigger 0 0 : one-shot mode 0 1 : repeat mode 1 0 : single sweep mode 1 1 : repeat sweep mode 0 / repeat sweep mode 1 (note 3) 0 : stop a-d conversion 1 : start a-d conversion b4 b3 notes 1: these bits are ignored in the single sweep and repeat sweep mode 0 and repeat sweep mode 1. (they may be either 0 or 1.) 2: when selecting an external trigger, the an 7 pin cannot be used as an analog input pin. 3: use the a-d operation mode select bit 1 (bit 2 at address 1f 16 ) to select either the repeat sweep mode 0 or repeat sweep mode 1. 4: writing to each bit (except bit 6) of the a-d control register 0 must be performed while the a-d converter halts. analog input select bits (valid in one-shot and repeat modes) (note 1) 3 7 6 5 undefined undefined rw rw rw rw rw rw rw rw 0 0 0 0 refer to table 8.2.1
a-d converter 7751 group users manual 8C5 (2) trigger select bit (bit 5) this bit is used to select the source of trigger occurrence. (refer to (3) a-d conversion start bit. ) (3) a-d conversion start bit (bit 6) l when internal trigger is selected setting this bit to 1 generates a trigger, causing the a-d converter to start operating. clearing this bit to 0 causes the a-d converter to stop operating. in the one-shot mode or single sweep mode, this bit is cleared to 0 after the operation is completed. in the repeat mode, repeat sweep mode 0 or repeat sweep mode 1, the a-d converter continues operating until this bit is cleared to 0 by software. l when external trigger is selected ______ when the ad trg pin level goes from h to l with this bit = 1, a trigger occurs, causing the a-d converter to start operating. the a-d converter stops when this bit is cleared to 0. in the one-shot mode or single sweep mode, this bit remains set to 1 even after the operation is completed. in the repeat mode, repeat sweep mode 0 or repeat sweep mode 1, the a-d converter continues operating until this bit is cleared to 0 by software. (4) a-d conversion frequency ( f ad ) select bit 0 (bit 7) the operating time of the a-d converter varies depending on the selected operating clock ( f ad ) by this bit and the a-d conversion frequency ( f ad ) select bit 1 (bit 4 at address 1f 16 ; refer to figure 8.2.3) as listed in table 8.2.3. since the a-d converters comparator consists of capacity coupling amplifiers, keep that f ad 3 250 khz during a-d conversion . 8.2 block description table 8.2.1 time for performance to one analog input pin (unit: s) 8-bit resolution 10-bit resolution 8-bit resolution 10-bit resolution clock source for peripheral devices select bit a-d conversion frequency ( f ad ) select bit 1 a-d conversion frequency ( f ad ) select bit 0 f ad f(x in ) = 25 mhz f(x in ) = 40 mhz 0 0 f 4 divided by 4 31.36 37.76 19.60 23.60 0 1 f 4 divided by 2 15.68 18.88 9.80 11.80 1 0 f 4 7.84 9.44 4.90 5.90 0 1 f 2 divided by 2 7.84 9.44 CCC CCC 1 0 f 2 3.92 4.72 CCC CCC 0 0 f 2 divided by 4 15.68 18.88 CCC CCC 0 1
a-d converter 7751 group users manual 8C6 8.2 block description 8.2.2 a-d control register 1 figure 8.2.3 shows the structure of the a-d control register 1. the a-d operation mode select bit 1 is used to select the operation mode of the a-d converter. the 8/10- bit mode select bit is used to select the resolution. refer to table 8.2.1 for the a-d conversion frequency ( f ad ) select bit 1. fig. 8.2.3 structure of a-d control register 1 (1) a-d sweep pin selection bits (bits 1 and 0) these bits are used to select analog input pins in the single sweep mode, repeat sweep mode 0 and repeat sweep mode 1. in the single sweep mode and repeat sweep mode 0, pins which are not selected as analog input pins function as programmable i/o ports. b7 b6 b5 b4 b3 b2 b1 b0 a-d control register 1 (address 1f 16 ) bit a-d conversion frequency ( f ad ) select bit 1 4 a-d operation mode select bit 1 (use in repeat sweep mode 0 and repeat sweep mode 1) (note 4) 2 1 0 bit name at reset 1 undefined rw functions refer to a-d conversion frequency ( f ad ) select bit 0 (bit 7 at address 1e 16 ) ; see table 8.2.1 0 : repeat sweep mode 0 1 : repeat sweep mode 1 notes 1: these bits are invalid in the one-shot and repeat modes. (they may be either 0 or 1.) 2: when selecting an external trigger, the an 7 pin cannot be used as an analog input pin. 3: analog input pins which are frequently a-d converted are selected in the repeat sweep mode 1. 4: fix this bit to 0 in the one-shot, repeat, and single sweep modes. 5: writing to each bit of the a-d control register 1 must be performed while the a-d converter halts. 3 7 to 5 rw rw 0 0 0 : an 0 , an 1 (2 pins) 0 1 : an 0 to an 3 (4 pins) 1 0 : an 0 to an 5 (6 pins) 1 1 : an 0 to an 7 (8 pins) (note 2) a-d sweep pin select bits (valid in single sweep, repeat sweep mode 0 and repeat sweep mode 1) (note 1) l single sweep mode/repeat sweep mode 0 b1 b0 0 0 : an 0 (1 pin) 0 1 : an 0 , an 1 (2 pins) 1 0 : an 0 to an 2 (3 pins) 1 1 : an 0 to an 3 (4 pins) l repeat sweep mode 1 (note 3) b1 b0 1rw 8/10-bit mode select bit 0 : 8-bit mode 1 : 10-bit mode rw 0 nothing is assigned. rw 0 C
a-d converter 7751 group users manual 8C7 8.2.3 a-d register i (i = 0 to 7) figure 8.2.4 shows the structure of the a-d register i. when the a-d conversion is completed, the conversion result (contents of the successive approximation register) is stored into this register. each a-d register i corresponds to an analog input pin (an i ). table 8.2.2 lists the correspondence of an analog input pin to a-d register i. 8.2 block description fig. 8.2.4 structure of a-d register i a-d register i where conversion result is stored a-d register 0 a-d register 1 a-d register 2 a-d register 3 a-d register 4 a-d register 5 a-d register 6 a-d register 7 table 8.2.2 correspondence of analog input pin and a-d register i analog input pin an 0 pin an 1 pin an 2 pin an 3 pin an 4 pin an 5 pin an 6 pin an 7 pin b7 b0 a-d register 0 (addresses 21 16 , 20 16 ) a-d register 1 (addresses 23 16 , 22 16 ) a-d register 2 (addresses 25 16 , 24 16 ) a-d register 3 (addresses 27 16 , 26 16 ) a-d register 4 (addresses 29 16 , 28 16 ) a-d register 5 (addresses 2b 16 , 2a 16 ) a-d register 6 (addresses 2d 16 , 2c 16 ) a-d register 7 (addresses 2f 16 , 2e 16 ) bit 7 to 0 at reset 0 undefined rw functions ro b7 b0 (b15) (b8) reads an a-d conversion result. 15 to 8 the value is 0 at reading. l 8-bit mode b7 b0 a-d register 0 (addresses 21 16 , 20 16 ) a-d register 1 (addresses 23 16 , 22 16 ) a-d register 2 (addresses 25 16 , 24 16 ) a-d register 3 (addresses 27 16 , 26 16 ) a-d register 4 (addresses 29 16 , 28 16 ) a-d register 5 (addresses 2b 16 , 2a 16 ) a-d register 6 (addresses 2d 16 , 2c 16 ) a-d register 7 (addresses 2f 16 , 2e 16 ) bit 9 to 0 at reset 0 undefined rw functions ro b7 b0 (b15) (b8) reads an a-d conversion result. 15 to 10 l 10-bit mode b2 (b10) ro ro the value is 0 at reading.
a-d converter 7751 group users manual 8C8 8.2.4 a-d conversion interrupt control register figure 8.2.5 shows the structure of the a-d conversion interrupt control register. for details about interrupts, refer to chapter 4. interrupts. 8.2 block description fig. 8.2.5 structure of a-d conversion interrupt control register (1) interrupt priority level select bits (bits 2 to 0) these bits select the a-d conversion interrupts priority level. when using a-d conversion interrupts, select priority levels 1 to 7. when an a-d conversion interrupt request occurs, its priority level is compared with the processor interrupt priority level (ipl) and the requested interrupt is enabled only when its priority level is higher than the ipl. (however, this applies when the interrupt disable flag (i) = 0.) to disable the a-d conversion interrupt, set these bits to 000 2 (level 0). (2) interrupt request bit (bit 3) this bit is set to 1 when an a-d conversion interrupt request occurs. this bit is automatically cleared to 0 when the a-d conversion interrupt request is accepted. this bit can be set to 1 or cleared to 0 by software. b7 b6 b5 b4 b3 b2 b1 b0 a-d conversion interrupt control register (address 70 16 ) bit 7 to 4 interrupt request bit 2 1 0 bit name at reset undefined (note) rw functions 0 0 0 : level 0 (interrupt disabled) 0 0 1 : level 1 low level 0 1 0 : level 2 0 1 1 : level 3 1 0 0 : level 4 1 0 1 : level 5 1 1 0 : level 6 1 1 1 : level 7 high level b2 b1 b0 0 : no interrupt request 1 : interrupt request interrupt priority level select bits 3 rw rw rw rw C undefined 0 0 0 nothing is assigned. note : clear the bit 3 to 0 by software when using a-d conversion interrupt.
a-d converter 7751 group users manual 8C9 8.2.5 port p7 direction register the a-d converter and port p7 use the same pins in common. when using these pins as the a-d converters input pins, set the corresponding bits of the port p7 direction register to 0 to set these ports for the input mode. figure 8.2.6 shows the relationship between the port p7 direction register and a-d converters input pins. 8.2 block description fig. 8.2.6 relationship between port p7 direction register and a-d converters input pins bit corresponding pin functions 0 1 2 3 4 5 6 7 an 0 pin 0 : input mode 1 : output mode when using these pins as a-d converters input pins, set the corresponding bits to 0. port p7 direction register (address 11 16 ) b1 b0 b2 b3 b4 b5 b6 b7 at reset rw 0 0 0 0 0 0 0 0 rw rw rw rw rw rw rw rw an 1 pin an 2 pin an 3 pin an 4 pin an 5 pin an 6 pin an 7 /ad trg pin
7751 group users manual 8C10 a-d converter 8.3 a-d conversion method (successive approximation conversion method) 8.3 a-d conversion method (successive approximation conversion method) the a-d converter compares the comparison voltage (v ref ), which is internally generated according to the contents of the successive approximation register, with the analog input voltage (v in ), which is input from the analog input pin (an i ). by reflecting the comparison result on the successive approximation register, v in is converted into a digital value. when a trigger is generated, the a-d converter performs the following processing: determining bit 9 of the successive approximation register the a-d converter compares v ref with v in . at this point, the contents of the successive approximation register are 1000000000 2 (initial value). bit 9 of the successive approximation register changes according to the comparison result as follows: when v ref < v in , bit 9 = 1 when v ref > v in , bit 9 = 0 determining bit 8 of the successive approximation register after setting bit 8 of the successive approximation register to 1, the a-d converter compares v ref with v in . bit 8 changes according to the comparison result as follows: when v ref < v in , bit 8 = 1 when v ref > v in , bit 8 = 0 a determining bits 7 to 0 of the successive approximation register operation in are performed for bits 7 to 0 in the 10-bit mode. operation in are performed for bits 7 to 2 in the 8-bit mode. when the lsb is determined, the contents (conversion result) of the successive approximation register are transferred to the a-d register i. the comparison voltage (v ref ) is generated according to the latest contents of the successive approximation register. table 8.3.1 lists the relationship between the successive approximation registers contents and v ref . table 8.3.2 and table 8.3.3 list changes of the successive approximation register and v ref during the a-d conversion. figure 8.3.1 shows the ideal a-d conversion characteristics in the 10-bit mode. table 8.3.1 relationship between successive approximation registers contents and v ref v ref ] 1024 successive approximation registers contents: n 0 1 to 1023 5 (n C 0.5) v ref (v) 0 v ref ] : reference voltage
7751 group users manual 8C11 a-d converter table 8.3.2 change in successive approximation register and v ref during a-d conversion in 8-bit mode 8.3 a-d conversion method (successive approximation conversion method) table 8.3.3 change in successive approximation register and v ref during a-d conversion in 10-bit mode 1 1 n 9 00000 0000 000 000000 100 000000 n 9 n 8 1000 0000 n 9 n 8 n 7 n 6 n 5 n 4 n 3 n 2 n 1 1 n 9 n 8 n 7 n 6 n 5 n 4 n 3 n 2 n 1 n 0 b9 b0 C 2 v ref 2048 v ref 2 v ref 2 v ref 4 v ref C 2048 v ref 2 v ref 4 v ref 8 v ref C 2048 v ref 2 v ref 4 v ref 8 v ref ...... v ref 1024 C 2048 v ref [v] [v] [v] [v] [v] successive approximation register a-d converter halt 1st comparison 2nd comparison 3rd comparison 10th comparison conversion complete 1st comparison result 2nd comparison result ?n 9 =1 ?n 9 =0 + C ?n 8 =1 ?n 8 =0 + C : : : : : : a-d converter halt 1st comparison 2nd comparison 3rd comparison 8th comparison conversion complete : : change of v ref 4 v ref 4 v ref 8 v ref 8 v ref 1 1 n 9 00000 0000 000 000000 100 000000 n 9 n 8 1000 0000 n 9 n 8 n 7 n 6 n 5 n 4 n 3 00 n 9 n 8 n 7 n 6 n 5 n 4 n 3 n 2 b9 b0 C 2 v ref 2048 v ref 2 v ref 2 v ref 4 v ref C 2048 v ref 2 v ref 4 v ref 8 v ref C 2048 v ref 2 v ref 4 v ref 8 v ref ...... v ref 256 C 2048 v ref [v] [v] [v] [v] [v] successive approximation register 1st comparison result 2nd comparison result ?n 9 =1 ?n 9 =0 + C ?n 8 =1 ?n 8 =0 + C : : : : change of v ref 4 v ref 4 v ref 8 v ref 8 v ref 00 1
7751 group users manual 8C12 a-d converter 8.3 a-d conversion method (successive approximation conversion method) fig. 8.3.1 ideal a-d conversion characteristics in 10-bit mode 000 16 001 16 002 16 003 16 3fe 16 3ff 16 analog input voltage v ref 1024 5 1 v ref 1024 5 2 v ref 1024 5 3 5 1021 v ref 1024 v ref 1024 5 1022 v ref 1024 5 1023 v ref v ref 1024 5 0.5 ldeal a-d conversion characteristics 0 a-d conversion result 3fd 16
7751 group users manual 8C13 a-d converter 8.4 absolute accuracy and differential non-linearity error 8.4.1 absolute accuracy the absolute accuracy is the difference expressed in the lsb between the actual a-d conversion result and the output code of an a-d converter with ideal characteristics. the analog input voltage when measuring the accuracy is assumed to be the mid point of the input voltage width that outputs the same output code from an a-d converter with ideal characteristics. for example, in the case of the 10-bit mode, when v ref =5.12 v, 1 lsb width is 5 mv, and 0 mv, 5 mv, 10 mv, 15 mv, 20 mv, ... are selected as the analog input voltages. the absolute accuracy = 3 lsb indicates that when the analog input voltage is 25 mv, the output code expected from an ideal a-d conversion characteristics is 005 16 , but the actual a-d conversion result is between 002 16 to 008 16 . the absolute accuracy includes the zero error and the full-scale error. the absolute accuracy degrades when v ref is lowered. the output code for analog input voltages v ref to av cc is 3ff 16 . fig. 8.4.1 absolute accuracy of a-d converter in 10-bit mode 8.4 absolute accuracy and differential non-linearity error 000 16 001 16 002 16 003 16 004 16 005 16 006 16 0 5 10 1520 253035 4045 5055 007 16 008 16 009 16 00a 16 00b 16 +3 lsb C3 lsb ideal a-d conversion characteristics analog input voltage (mv) output code (a-d conversion result)
7751 group users manual 8C14 a-d converter 8.4.2 differential non-linearity error the differential non-linearity error indicates the difference between the 1 lsb step width (the ideal analog input voltage width while the same output code is expected to output) of an a-d converter with ideal characteristics and the actual measured step width (the actual analog input voltage width while the same output code is output). for example, in the case of the 10-bit mode, when v ref =5.12 v, the 1 lsb width of an a-d converter with ideal characteristics is 5 mv, but if the differential non-linearity error is 1 lsb, the actual measured 1 lsb width is 0 to 10 mv. fig. 8.4.2 differential non-linearity error in 10-bit mode 8.4 absolute accuracy and differential non-linearity error 000 16 001 16 002 16 003 16 004 16 005 16 006 16 0 5 10 1520 253035 4045 007 16 008 16 009 16 output code (a-d conversion result) differential non-linearity error analog input voltage (mv) 1 lsb width with ideal a-d conversion characteristics
7751 group users manual 8C15 a-d converter 8.5 comparison voltage in 8-bit mode in the 8-bit mode, the m37751 treats the high-order 8 bits of the 10-bit successive approximation register as the conversion result. accordingly, when compared with the 8-bit a-d converter, the a-d conversion of the m37751 is performed by using a comparison reference voltage that is different by 3v ref /2048 (refer to the underlined portions in the table 8.5.1). the difference of the output code change point is generated as shown in figure 8.5.1. m37751s 8-bit mode 8-bit a-d converter comparison reference voltage v ref v ref /2 8 5 n v ref /2 10 5 0.5 v ref /2 8 5 n v ref /2 8 5 0.5 v ref : reference voltage n : contents of successive approximation register table 8.5.1 comparison reference voltage of the m37751s 8-bit mode and 8-bit a-d converter 8.5 comparison voltage in 8-bit mode fig. 8.5.1 difference of output code change point 07 05 06 03 00 02 analog input voltage (mv) 02 01 00 04 02 01 00 01 08 09 10 30 17.5 37.5 l 8-bit a-d converter with ideal characteristics (in the case of v ref = 5.12 v) output code (a-d conversion result) l m37751s a-d converter with ideal characteristics (in the case of v ref = 5.12 v) output code (a-d conversion result) 8-bit mode 10-bit mode ( note ) analog input voltage (mv) 8-bit mode 10-bit mode note : difference from output code change point v ref : reference voltage ( note )
7751 group users manual 8C16 a-d converter 8.6 one-shot mode 8.6 one-shot mode in the one-shot mode, the operation for the input voltage from the one selected analog input pin is performed once, and an a-d conversion interrupt request occurs when the operation is completed. 8.6.1 settings for one-shot mode figure 8.6.1 shows an initial setting example of the one-shot mode. when using an interrupt, it is necessary to set the corresponding register to enable interrupts. refer to chapter 4. interrupts for more descriptions.
7751 group users manual 8C17 a-d converter 8.6 one-shot mode fig. 8.6.1 initial setting example of one-shot mode l interrupt priority level b7 b0 a-d conversion interrupt control register (address 70 16 ) interrupt priority level select bits set to a level between 1 to 7 when using this interrupt. set to a level 0 when disabling this interrupt. interrupt request bit 0 : no interrupt request b7 b0 port p7 direction register (address 11 16 ) l port p7 direction register set the bits corresponding to analog input pins to 0. set bit 7 to 0 when selecting external trigger. l set a-d conversion start bit to 1 b7 b0 a-d control register 0 (address 1e 16 ) 1 a-d conversion start bit selecting external trigger selecting internal trigger input falling edge to ad trg pin trigger occur operation start note: write the following registers when the a-d conversion stops (before trigger occurs). ? each bit of a-d control register 0 (except bit 6) ? each bit of a-d control register 1 0 an 1 an 2 an 3 an 5 an 6 an 7 an 4 an 0 b7 b0 a-d control register 0 (address 1e 16 ) 00 0 0 0 0 : an 0 selected 0 0 1 : an 1 selected 0 1 0 : an 2 selected 0 1 1 : an 3 selected 1 0 0 : an 4 selected 1 0 1 : an 5 selected 1 1 0 : an 6 selected 1 1 1 : an 7 selected b1 b0 b2 trigger select bit 0 : internal trigger 1 : external trigger a-d conversion start bit 0 : stop a-d conversion analog input select bits 8/10-bit mode select bit 0 : 8-bit mode 1 : 10-bit mode a-d conversion frequency ( f ad ) select bit 0 a-d conversion frequency ( f ad ) select bit 1 = 0 0 : f 2 /f 4 divided by 4 1 : f 2 /f 4 divided by 2 a-d conversion frequency ( f ad ) select bit 1 = 1 0 : f 2 /f 4 1 : not selected b7 b0 l a-d control register 0 and a-d control register 1 a-d control register 1 (address 1f 16 ) 0 55 5 : 0 or 1 a-d conversion frequency ( f ad ) select bit 1 refer to a-d conversion frequency ( f ad ) select bit 0. one-shot mode
7751 group users manual 8C18 a-d converter 8.6 one-shot mode 8.6.2 one-shot mode operation description (1) when an internal trigger is selected the a-d converter starts operation when the a-d conversion start bit is set to 1. the a-d conversion is completed after 49 cycles of f ad in the 8-bit mode, or 59 cycles of f ad in the 10-bit mode. then, the contents of the successive approximation register (conversion result) are transferred to the a-d register i. a at the same time as step , the a-d conversion interrupt request bit is set to 1. ? the a-d conversion start bit is cleared to 0 and the a-d converter stops operation. (2) when an external trigger is selected ______ the a-d converter starts operation when the input level to the ad trg pin changes from h to l while the a-d conversion start bit is 1. the a-d conversion is completed after 49 cycles of f ad in the 8-bit mode, or 59 cycles of f ad in the 10-bit mode. then, the contents of the successive approximation register (conversion result) are transferred to the a-d register i. a at the same time as step , the a-d conversion interrupt request bit is set to 1. ? the a-d conversion stops operation. the a-d conversion start bit remains set to 1 after the operation is completed. accordingly, the ______ operation of the a-d converter can be performed again from step when the level of the ad trg pin changes from h to l. ______ when the level of the ad trg pin changes from h to l during operation, the operation at that point is cancelled and is restarted from step . figure 8.6.2 shows the conversion operation in the one-shot mode.
7751 group users manual 8C19 a-d converter 8.6 one-shot mode trigger occur convert input voltage from an i pin a-d converter halt a-d converter interrupt request occur conversion result a-d register i fig. 8.6.2 conversion operation in one-shot mode
7751 group users manual 8C20 a-d converter 8.7 repeat mode 8.7 repeat mode in the repeat mode, the operation for the input voltage from the one selected analog input pin is performed repeatedly. in this mode, no a-d conversion interrupt request occurs. additionally, the a-d conversion start bit (bit 6 at address 1e 16 ) remains set to 1 until it is cleared to 0 by software, and the operation is performed repeatedly while the a-d conversion start bit is 1. 8.7.1 settings for repeat mode figure 8.7.1 shows an initial setting example of repeat mode.
7751 group users manual 8C21 a-d converter 8.7 repeat mode fig. 8.7.1 initial setting example of repeat mode b7 b0 port p7 direction register (address 11 16 ) l port p7 direction register set the bits corresponding to analog input pins to 0. set bit 7 to 0 when selecting external trigger. l set a-d conversion start bit to 1 b7 b0 a-d control register 0 (address 1e 16 ) 1 a-d conversion start bit selecting external trigger selecting internal trigger input falling edge to ad trg pin trigger occur operation start note: write the following registers when the a-d conversion stops (before trigger occurs). ? each bit of a-d control register 0 (except bit 6) ? each bit of a-d control register 1 an 0 an 1 an 2 an 3 an 4 an 5 an 6 an 7 b7 b0 a-d control register 0 (address 1e 16 ) 01 0 0 0 0 : an 0 selected 0 0 1 : an 1 selected 0 1 0 : an 2 selected 0 1 1 : an 3 selected 1 0 0 : an 4 selected 1 0 1 : an 5 selected 1 1 0 : an 6 selected 1 1 1 : an 7 selected b1 b0 b2 trigger select bit 0 : internal trigger 1 : external trigger a-d conversion start bit 0: stop a-d conversion analog input select bits 8/10-bit mode select bit 0 : 8-bit mode 1 : 10-bit mode a-d conversion frequency ( f ad ) select bit 0 a-d conversion frequency ( f ad ) select bit 1 = 0 0 : f 2 /f 4 divided by 4 1 : f 2 /f 4 divided by 2 a-d conversion frequency ( f ad ) select bit 1 = 1 0 : f 2 /f 4 1 : not selected b7 b0 0 55 l a-d control register 0 and a-d control register 1 a-d control register 1 (address 1f 16 ) 5 : 0 or 1 a-d conversion frequency ( f ad ) select bit 1 refer to a-d conversion frequency ( f ad ) select bit 0. repeat mode
7751 group users manual 8C22 a-d converter 8.7 repeat mode 8.7.2 repeat mode operation description (1) when an internal trigger is selected the a-d converter starts operation when the a-d conversion start bit is set to 1. the first a-d conversion is completed after 49 cycles of f ad in the 8-bit mode, or 59 cycles of f ad in the 10-bit mode. then, the contents of the successive approximation register (conversion result) are transferred to the a-d register i. a the a-d converter repeats operation until the a-d conversion start bit is cleared to 0 by software. the conversion result is transferred to the a-d register i each time the conversion is completed. (2) when an external trigger is selected ______ the a-d converter starts operation when the input level to the ad trg pin changes from h to l while the a-d conversion start bit is 1. the first a-d conversion is completed after 49 cycles of f ad in the 8-bit mode, or 59 cycles of f ad in the 10-bit mode. then, the contents of the successive approximation register (conversion result) are transferred to the a-d register i. a the a-d converter repeats operation until the a-d conversion start bit is cleared to 0 by software. the conversion result is transferred to the a-d register i each time the conversion is completed. when the comparator function is selected, the comparison result is stored in the an i pin comparator result bit each time the comparison is completed. ______ when the level of the ad trg pin changes from h to l during operation, the operation at that point is cancelled and is restarted from step . figure 8.7.2 shows the conversion operation in the repeat mode. fig. 8.7.2 conversion operation in repeat mode trigger occur convert input voltage from an i pin conversion result a-d register i
7751 group users manual 8C23 a-d converter 8.8 single sweep mode in the single sweep mode, the operation for the input voltage from multiple selected analog input pins is performed, one at a time. the a-d converter is operated in ascending sequence from the an 0 pin. an a-d conversion interrupt request occurs when the operation for all selected input pins are completed. 8.8.1 settings for single sweep mode figure 8.8.1 shows an initial setting example of single sweep mode. when using an interrupt, it is necessary to set the corresponding register to enable interrupts. refer to chapter 4. interrupts for more information. 8.8 single sweep mode
7751 group users manual 8C24 a-d converter 8.8 single sweep mode fig. 8.8.1 initial setting example of single sweep mode b7 b0 port p7 direction register (address 11 16 ) l port p7 direction register set the bits corresponding to analog input pins to 0. set bit 7 to 0 when selecting external trigger. l interrupt priority level b7 b0 a-d conversion interrupt control register (address 70 16 ) interrupt priority level select bits set to a level between 1 to 7 when using this interrupt. set to a level 0 when disabling this interrupt. interrupt request bit 0 : no interrupt request note: write the following registers when the a-d conversion stops (before trigger occurs). ? each bit of a-d control register 0 (except bit 6) ? each bit of a-d control register 1 l set a-d conversion start bit to 1 b7 b0 a-d control register 0 (address 1e 16 ) 1 a-d conversion start bit selecting external trigger selecting internal trigger trigger occur operation start input falling edge to ad trg pin 0 an 0 an 1 an 2 an 3 an 4 an 5 an 6 an 7 a-d control register 0 (address 1e 16 ) 0 0 : an 0 , an 1 (2 pins) 0 1 : an 0 to an 3 (4 pins) 1 0 : an 0 to an 5 (6 pins) 1 1 : an 0 to an 7 (8 pins) b1 b0 trigger select bit 0 : internal trigger 1 : external trigger a-d conversion start bit 0: stop a-d conversion 8/10-bit mode select bit 0 : 8-bit mode 1 : 10-bit mode a-d conversion frequency ( f ad ) select bit 0 a-d conversion frequency ( f ad ) select bit 1 = 0 0 : f 2 /f 4 divided by 4 1 : f 2 /f 4 divided by 2 a-d conversion frequency ( f ad ) select bit 1 = 1 0 : f 2 /f 4 1 : not selected b7 b0 0 l a-d control register 0 and a-d control register 1 a-d control register 1 (address 1f 16 ) b7 b0 10 0 55 5 a-d sweep pin select bits 5 : 0 or 1 a-d conversion frequency ( f ad ) select bit 1 refer to a-d conversion frequency ( f ad ) select bit 0. single sweep mode
7751 group users manual 8C25 a-d converter 8.8.2 single sweep mode operation description (1) when an internal trigger is selected the a-d converter starts conversion for the input voltage from the an 0 pin starts when the a-d conversion start bit is set to 1. the a-d conversion of the input voltage from the an 0 pin is completed after 49 cycles of f ad in the 8-bit mode, or 59 cycles of f ad in the 10-bit mode. then, the contents of the successive approximation register (conversion result) are transferred to the a-d register 0. a the operation to all selected analog input pins is performed. the conversion result is transferred to the a-d register i each time each pin is converted. ? when the step a is completed, the a-d conversion interrupt request bit is set to 1. ? the a-d conversion start bit is cleared to 0 and the a-d converter stops operation. (2) when an external trigger is selected the a-d converter starts conversion for the input voltage from the an 0 pin when the input level to ______ the ad trg pin changes from h to l while the a-d conversion start bit is 1. the a-d conversion of the input voltage from the an 0 pin is completed after 49 cycles of f ad in the 8-bit mode, or 59 cycles of f ad in the 10-bit mode. then, the contents of the successive approximation register (conversion result) are transferred to the a-d register 0. a the operation to all selected analog input pins is performed. the conversion result is transferred to the a-d register i each time each pin is converted. ? when the step a is completed, the a-d conversion interrupt request bit is set to 1. ? the a-d conversion stops operation. the a-d conversion start bit remains set to 1 after the operation is completed. accordingly, the ______ operation of the a-d converter can be performed again from step when the level of the ad trg pin changes from h to l. ______ when the level of the ad trg pin changes from h to l during operation, the operation at that point is cancelled and is restarted from step . figure 8.8.2 shows the conversion operation in the single sweep mode. 8.8 single sweep mode
7751 group users manual 8C26 a-d converter 8.8 single sweep mode fig. 8.8.2 conversion operation in single sweep mode trigger occur convert input voltage from an 0 pin conversion result a-d register 0 a-d register i a-d register 1 conversion result conversion result a-d converter halt a-d converter interrupt request occur convert input voltage from an 1 pin convert input voltage from an i pin
7751 group users manual 8C27 a-d converter 8.9 repeat sweep mode 0 in the repeat sweep mode 0, the operation for the input voltage from the multiple selected analog input pins is performed repeatedly. the a-d converter is operated in ascending sequence from the an 0 pin. in this mode, no a-d conversion interrupt request occurs. additionally, the a-d conversion start bit (bit 6 at address 1e 16 ) remains set to 1 until it is cleared to 0 by software, and the operation is performed repeatedly while the a-d conversion start bit is 1. 8.9.1 settings for repeat sweep mode 0 figure 8.9.1 shows an initial setting example of repeat sweep mode 0. 8.9 repeat sweep mode 0
7751 group users manual 8C28 a-d converter 8.9 repeat sweep mode 0 fig. 8.9.1 initial setting example of repeat sweep mode 0 l set a-d conversion start bit to 1 b7 b0 a-d control register 0 (address 1e 16 ) 1 a-d conversion start bit selecting external trigger selecting internal trigger input falling edge to ad trg pin trigger occur operation start note: write the following registers when the a-d conversion stops (before trigger occurs). ? each bit of a-d control register 0 (except bit 6) ? each bit of a-d control register 1 b7 b0 port p7 direction register (address 11 16 ) l port p7 direction register set the bits corresponding to analog input pins to 0. set bit 7 to 0 when selecting external trigger. an 0 an 1 an 2 an 3 an 4 an 5 an 6 an 7 a-d control register 0 (address 1e 16 ) 0 0 : an 0 , an 1 (2 pins) 0 1 : an 0 to an 3 (4 pins) 1 0 : an 0 to an 5 (6 pins) 1 1 : an 0 to an 7 (8 pins) b1 b0 trigger select bit 0 : internal trigger 1 : external trigger a-d conversion start bit 0: stop a-d conversion 8/10-bit mode select bit 0 : 8-bit mode 1 : 10-bit mode a-d conversion frequency ( f ad ) select bit 0 a-d conversion frequency ( f ad ) select bit 1 = 0 0 : f 2 /f 4 divided by 4 1 : f 2 /f 4 divided by 2 a-d conversion frequency ( f ad ) select bit 1 = 1 0 : f 2 /f 4 1 : not selected b7 b0 l a-d control register 0 and a-d control register 1 a-d control register 1 (address 1f 16 ) b7 b0 a-d sweep pin select bits 5 : 0 or 1 0 a-d conversion frequency ( f ad ) select bit 1 refer to a-d conversion frequency ( f ad ) select bit 1. repeat sweep mode 0 repeat sweep mode 0 11 0 55 5
7751 group users manual 8C29 a-d converter 8.9.2 repeat sweep mode 0 operation description (1) when an internal trigger is selected the a-d converter starts conversion for the input voltage from the an 0 pin starts when the a-d conversion start bit is set to 1. the a-d conversion of the input voltage from the an 0 pin is completed after 49 cycles of f ad in the 8-bit mode, or 59 cycles of f ad in the 10-bit mode. then, the contents of the successive approximation register (conversion result) are transferred to the a-d register 0. a the operation to all selected analog input pins is performed. the conversion result is transferred to the a-d register i each time each pin is converted. ? the operation to all selected analog input pins is performed again. ? the operation is performed repeatedly until the a-d conversion start bit is cleared to 0 by software. (2) when an external trigger is selected the a-d converter starts conversion for the input voltage from the an 0 pin when the input level to ______ the ad trg pin changes from h to l while the a-d conversion start bit is 1. the a-d conversion of the input voltage from the an 0 pin is completed after 49 cycles of f ad in the 8-bit mode, or 59 cycles of f ad in the 10-bit mode. then, the contents of the successive approximation register (conversion result) are transferred to the a-d register 0. a the operation to all selected analog input pins is performed. the conversion result is transferred to the a-d register i each time each pin is converted. ? the operation to all selected analog input pins is performed again. ? the operation is performed repeatedly until the a-d conversion start bit is cleared to 0 by software. ______ when the level of the ad trg pin changes from h to l during operation, the operation at that point is cancelled and is restarted from step . figure 8.9.2 shows the conversion operation in the repeat sweep mode 0. 8.9 repeat sweep mode 0
7751 group users manual 8C30 a-d converter 8.9 repeat sweep mode 0 fig. 8.9.2 conversion operation in repeat sweep mode 0 trigger occur convert input voltage from an 0 pin conversion result a-d register 0 a-d register i a-d register 1 conversion result conversion result convert input voltage from an 1 pin convert input voltage from an i pin
7751 group users manual 8C31 a-d converter 8.10 repeat sweep mode 1 in the repeat sweep mode 1, the operation for the input voltage from all selected analog input pins is performed repeatedly. in this mode, analog input pins are separated into two groups according to the frequency of use. one is the group for more frequencies of use. the other is the group for few frequencies of use. first, the operations to all analog input pins in the group of more frequencies of use are performed. next, the operation to one of analog input pins in the group of fewer frequencies of use is operated. figure 8.10.1 shows the analog input pin sweep operation. as shown in figure 8.10.1, the pin to be executed in the group of fewer frequencies changes sequently. in this mode, no a-d conversion interrupt request occurs. additionally, the a-d conversion start bit (bit 6 at address 1e 16 ) remains set to 1 until it is cleared to 0 by software, and the operation is performed repeatedly while the a-d conversion start bit is 1. 8.10.1 settings for repeat sweep mode 1 figure 8.10.2 shows an initial setting example of repeat sweep mode 1. select the analog input pins in the group of more frequencies of use by the a-d sweep pin select bits (bits 1 and 0 at address 1f 16 ). pins which are not selected by the a-d sweep pin select bits belong to the group of fewer frequencies of use. 8.10 repeat sweep mode 1
7751 group users manual 8C32 a-d converter 8.10 repeat sweep mode 1 fig. 8.10.1 analog input pin sweep operation in repeat sweep mode 1 l a-d sweep pin select bit: bits 1, 0 at address 1f 16 = 00 2 (group of more frequencies of use: an 0 pin) an 0 an 0 an 1 an 0 an 2 an 0 an 3 an 0 an 4 an 0 an 5 an 0 an 6 ???????????? an 0 an 1 an 0 an 2 an 7 ? ?? ?? ? l a-d sweep pin select bit: bits 1, 0 at address 1f 16 = 01 2 (group of more frequencies of use: pins an 0 and an 1 ) an 0 an 1 an 0 an 1 an 2 an 0 an 1 an 3 an 0 an 1 an 4 an 0 an 1 an 5 an 0 an 1 an 6 an 0 an 1 an 7 ???????????? ? ? ? ? ? ? ? an 2 an 0 an 1 an 3 ? ?? ? ? l a-d sweep pin select bit: bits 1, 0 at address 1f 16 = 10 2 (group of more frequencies of use: pins an 0 Can 2 ) an 0 an 1 an 2 an 0 an 1 an 2 an 3 an 0 an 1 an 2 an 4 an 0 an 1 an 2 an 5 an 0 an 1 an 2 an 6 an 0 an 1 an 2 an 7 an 0 an 1 an 2 an 3 ???????????? ? ? ? ? ? ? ? an 4 ? ? ? l a-d sweep pin select bit: bits 1, 0 at address 1f 16 = 11 2 (group of more frequencies of use: pins an 0 Can 3 ) an 0 an 1 an 2 an 3 an 4 an 0 an 1 an 2 an 3 an 5 an 0 an 1 an 2 an 3 an 6 an 0 an 1 an 2 an 3 an 7 an 0 an 1 an 2 an 3 an 4 an 0 an 1 an 2 an 3 an 5 ???????????? ? ? ? ? ? ?? ? ? ? ? ? ? ? ?? ?? ?? ?? ?? ......... ......... ......... ......... ? : this symbol expresses the order of performance : group of more frequencies of use
7751 group users manual 8C33 a-d converter 8.10 repeat sweep mode 1 fig. 8.10.2 initial setting example of repeat sweep mode 1 b7 b0 port p7 direction register (address 11 16 ) l port p7 direction register set the bits corresponding to analog input pins to 0. set bit 7 to 0 when selecting external trigger. l set a-d conversion start bit to 1 b7 b0 a-d control register 0 (address 1e 16 ) 1 a-d conversion start bit selecting external trigger selecting internal trigger input falling edge to ad trg pin trigger occur operation start note: write the following registers when the a-d conversion stops (before trigger occurs). ? each bit of a-d control register 0 (except bit 6) ? each bit of a-d control register 1 an 0 an 1 an 2 an 3 an 4 an 5 an 6 an 7 a-d control register 0 (address 1e 16 ) 0 0 : an 0 (1 pin) 0 1 : an 0 , an 1 (2 pins) 1 0 : an 0 to an 2 (3 pins) 1 1 : an 0 to an 3 (4 pins) b1 b0 trigger select bit 0 : internal trigger 1 : external trigger a-d conversion start bit 0: stop a-d conversion 8/10-bit mode select bit 0 : 8-bit mode 1 : 10-bit mode a-d conversion frequency ( f ad ) select bit 0 a-d conversion frequency ( f ad ) select bit 1 = 0 0 : f 2 /f 4 divided by 4 1 : f 2 /f 4 divided by 2 a-d conversion frequency ( f ad ) select bit 1 = 1 0 : f 2 /f 4 1 : not selected l a-d control register 0 and a-d control register 1 a-d control register 1 (address 1f 16 ) b7 b0 11 0 55 5 a-d sweep pin select bits 5 : 0 or 1 b7 b0 1 a-d conversion frequency ( f ad ) select bit 1 refer to a-d conversion frequency ( f ad ) select bit 0 . repeat sweep mode 1 repeat sweep mode 1
7751 group users manual 8C34 a-d converter 8.10 repeat sweep mode 1 8.10.2 repeat sweep mode 1 operation description (1) when an internal trigger is selected the a-d converter starts conversion for the input voltage from the an 0 pin when the a-d conversion start bit is set to 1. the a-d conversion of the input voltage from the an 0 pin is completed after 49 cycles of f ad in the 8-bit mode, or 59 cycles of f ad in the 10-bit mode. then, the contents of the successive approximation register (conversion result) are transferred to the a-d register 0. a the operations to all analog input pins in the group of more frequencies of use are performed. the conversion result is transferred to the a-d register i each time each pin is converted. ? the operation to one (refer to figure 8.10.1) of analog input pins in the group of fewer frequencies of use is performed. ? the operations to all analog input pins in the group of more frequencies of use are performed again. ? the operation to another one, which is different from the one selected in step ? , of analog input pins in the group of fewer frequencies of use is performed. (refer to figure 8.10.1.) ? the operation is performed repeatedly until the a-d conversion start bit is cleared to 0 by software. (2) when an external trigger is selected the a-d converter starts conversion for the input voltage from the an 0 pin when the input level to ______ the ad trg pin changes from h to l while the a-d conversion start bit is set to 1. the a-d conversion of the input voltage from the an 0 pin is completed after 49 cycles of f ad in the 8-bit mode, or 59 cycles of f ad in the 10-bit mode. then, the contents of the successive approximation register (conversion result) are transferred to the a-d register 0. a the operations to all analog input pins in the group of more frequencies of use are performed. the conversion result is transferred to the a-d register i each time each pin is converted. ? the operation to one (refer to figure 8.10.1) of analog input pins in the group of fewer frequencies of use is performed. ? the operations to all analog input pins in the group of more frequencies of use are performed again. ? the operation to another one, which is different from the one selected in step ? , of analog input pins in the group of fewer frequencies of use is performed. (refer to figure 8.10.1.) ? the operation is performed repeatedly until the a-d conversion start bit is cleared to 0 by software. ______ when the level of the ad trg pin changes from h to l during operation, the operation at that point is cancelled and is restarted from step .
7751 group users manual 8C35 a-d converter [precautions when using a-d converter] [precautions when using a-d converter] 1. write to the following bits and registers before a trigger occurs (while the a-d converter stops operation). ? a-d control register 0 (except bit 6) ? a-d control register 1 ______ 2. when an external trigger is selected, the an 7 / ad trg pin cannot be used as the analog input pin. it is ______ because the an 7 / ad trg pin is not connected to the comparator. when an external trigger is selected and the an 7 pin is selected as the analog input pin, the a-d converter is operated and the a-d register 7 contains an undefined value. 3. refer to appendix.8 examples of noise immunity improvement when using the a-d converter.
7751 group users manual 8C36 a-d converter [precautions when using a-d converter] memorandum
chapter 9 watchdog timer 9.1 block description 9.2 operation description 9.3 precautions when using watchdog timer
watchdog timer 7751 group users manual 9C2 9.1 block description this chapter describes watchdog timer. watchdog timer has the following functions: l detection of a program runaway. l measurement of a certain time when oscillation starts owing to terminating stop mode. (refer to chapter 10. stop mode. ) 9.1 block description figure 9.1.1 shows the block diagram of the watchdog timer. fig. 9.1.1 block diagram of watchdog timer 2v cc detection circuit fff 16 is set. writing to watchdog timer register (address 60 16 ) stp instruction hold request watchdog timer interrupt request reset s q r f 2 /f 4 watchdog timer 1/16 1/16 wf 32 /wf 64 wf 512 /wf 1024 watchdog timer frequency select bit
watchdog timer 7751 group users manual 9C3 9.1.1 watchdog timer watchdog timer is a 12-bit counter that down-counts the count source which is selected with the watchdog timer frequency select bit (bit 0 at address 61 16 ). a value fff 16 is automatically set in watchdog timer in the cases listed below. an arbitrary value cannot be set to watchdog timer. l when dummy data is written to the watchdog timer register (refer to figure 9.1.2.) l when the most significant bit of watchdog timer becomes 0 l when the stp instruction is executed (refer to chapter 10. stop mode. ) l at reset 9.1 block description fig. 9.1.2 structure of watchdog timer register b7 b0 watchdog timer register (address 60 16 ) bit initializes the watchdog timer. when a dummy data is written to this register, the watchdog timers value is initialized to fff 16 . (dummy data: 00 16 to ff 16 ) at reset undefined rw functions 7 to 0 C
watchdog timer 7751 group users manual 9C4 9.1.2 watchdog timer frequency select register this is used to select the watchdog timers count source. figure 9.1.3 shows the structure of the watchdog timer frequency select register. fig. 9.1.3 structure of watchdog timer frequency select register 9.1 block description 0 : wf 512 /wf 1024 1 : wf 32 /wf 64 at reset undefined 0 rw functions b7 b6 b5 b4 b3 b2 b1 b0 watchdog timer frequency select register (address 61 16 ) bit nothing is assigned. watchdog timer frequency select bit bit name 0 7 to 1 rw C
watchdog timer 7751 group users manual 9C5 9.2 operation description table 9.2.1 occurrence interval of watchdog timer interrupt request watchdog timer frequency select bit 0 1 occurrence interval 83.89 ms 5.24 ms count source wf 1024 wf 64 f(x in ) = 25 mhz 9.2 operation description the operation of watchdog timer is described below. 9.2.1 basic operation watchdog timer starts down-counting from fff 16 . when the watchdog timers most significant bit becomes 0 (counted 2048 times), the watchdog timer interrupt request occurs. (refer to table 9.2.1.) a when the interrupt request occurs at above , a value fff 16 is set to watchdog timer. the watchdog timer interrupt is a nonmaskable interrupt. when the watchdog timer interrupt request is accepted, the processor interrupt priority level (ipl) is set to 111 2 . clock source for peripheral devices select bit = 1 clock source for peripheral devices select bit = 0 occurrence interval 41.94 ms 2.62 ms count source wf 512 wf 32 clock source for peripheral devices select bit = 0 f(x in ) = 40 mhz count source wf 1024 wf 64 occurrence interval 52.43 ms 3.28 ms clock source for peripheral devices select bit : bit 2 at address 5f 16
watchdog timer 7751 group users manual 9C6 (1) example of program runaway detection write to the address 60 16 (watchdog timer register) before the most significant bit of watchdog timer becomes 0. in the case that watchdog timer is used to detect a program runaway, if writing to address 60 16 is not performed owing to a program runaway, the watchdog timer interrupt request occurs when the most significant bit of watchdog timer becomes 0. it means that a program runaway has occurred. to reset the microcomputer after a program runaway, write 1 to the software reset bit (bit 3 at address 5e 16 ) in the watchdog timer interrupt routine. 9.2 operation description fig. 9.2.1 example of program runaway detection by watchdog timer rti main routine watchdog timer interrupt routine watchdog timer register (address 60 16 ) 8-bit dummy data watchdog timer interrupt request occur (program runaway detected) watchdog timer initialized value of watchdog timer : fff 16 ( note 1 ) software reset bit (address 5e 16 , b3) 1 ( note 2 ) reset microcomputer notes 1: initialize (write to address 60 16 ) watchdog timer before the most significant bit of watchdog timer becomes 0 (the watchdog timer interrupt request occurs). 2: when the program runaway occurs, values of the data bank register (dt) and direct page register (dpr) may be changed. when 1 is written to the software reset bit by the addressing mode using dt and dpr, set values to dt and dpr again.
watchdog timer 7751 group users manual 9C7 9.2.2 operation in stop mode in stop mode, watchdog timer stops operating. immediately after stop mode is terminated, watchdog timer operates as follows. (1) when stop mode is terminated by a hardware reset supply of the f cpu and f biu starts immediately after stop mode is terminated, and the microcomputer performs the operation after a reset. (refer to chapter 13. reset. ) the watchdog timer frequency select bit becomes 0, and watchdog timer starts counting of wf 1024 from fff 16 . (2) when stop mode is terminated by an interrupt request occurrence immediately after stop mode is terminated, watchdog timer starts counting of the count source wf 32 / wf 64 from fff 16 . supply of the f cpu and f biu starts when the watchdog timers most significant bit becomes 0. ( at this time, the watchdog timer interrupt request does not occur.) supply of the f cpu and f biu starts immediately after stop mode is terminated, and the microcomputer executes the routine of the interrupt which is used to terminate stop mode. watchdog timer restarts counting of the count source (note) from fff 16 . note: clock wf 32 /wf 64 or wf 512 /wf 1024 which was counted just before executing the stp instruction. 9.2.3 operation in hold state watchdog timer stops operating in hold state. when hold state ] is terminated, watchdog timer restarts counting in the same state where it stopped operating. hold state ] : refer to section 12.4 hold function. 9.2 operation description
watchdog timer 7751 group users manual 9C8 9.3 precautions when using watchdog timer 9.3 precautions when using watchdog timer 1. when a dummy data is written to address 60 16 with the 16-bit data length, writing to address 61 16 is simultaneously performed. accordingly, when the user does not want to change a value of the watchdog timer frequency select bit (bit 0 at address 61 16 ), write the previous value to the bit simultaneously with writing to address 60 16 . 2. when the stp instruction (refer to chapter 10. stop mode ) is executed, watchdog timer stops. when watchdog timer is used to detect the program runaway, select stp instruction disable with mask option.
chapter 10 stop mode 10.1 clock generating circuit 10.2 operation description 10.3 precautions for stop mode
7751 group users manual stop mode 10C2 this chapter describes stop mode. stop mode is used to stop oscillation when there is no need to operate the central processing unit (cpu). the microcomputer enters stop mode when the stp instruction is executed. stop mode can be terminated by an interrupt request occurrence or the hardware reset. 10.1 clock generating circuit figure 10.1.1 shows the clock generating circuit. 10.1 clock generating circuit fig. 10.1.1 clock generating circuit q x in x out r s q r s q r s 1 biu cpu 1/8 f 2 /f 4 1/4 1/8 f 16 /f 32 f 64 /f 128 f 512 /f 1024 wf 512 /wf 1024 interrupt request stp instruction reset wit instruction ready request request of cpu wait from biu operation clock for internal peripheral devices watchdog timer (note) watchdog timer frequency select bit 1/2 1/2 0 1 hold request 1/16 1/16 wf 32 /wf 64 1 0 clock source for peripheral devices select bit clock source for peripheral devices select bit : bit 2 at address 5f 16 watchdog timer frequency select bit : bit 0 at address 61 16 cpu : central processing unit biu : bus interface unit note : this is the signal generated when the watchdog timers most significant bit becomes 0.
stop mode 7751 group users manual 10C3 10.2 operation description 10.2 operation description when the stp instruction is executed, the oscillator stops oscillating. this state is called stop mode. in stop mode, the contents of the internal ram can be retained intact when the vcc, power source voltage, is 2 v or more. additionally, the microcomputers power consumption is reduced. it is because the cpu and all internal peripheral devices using clocks f 2 /f 4 to f 512 /f 1024 stop the operation. table 10.2.1 lists the microcomputer state and operation in and after stop mode. table 10.2.1 microcomputer state and operation in and after stop mode state and operation item stopped operating enabled only in event counter mode operating enabled only when selecting external clock stopped retains the same state in which the stp instruction was executed by interrupt request occurrence by hardware reset oscillation f cpu , f biu , f , clock f 1 , f 2 /f 4 to f 512 /f 1024 , wf 32 /wf 64 , wf 512 /wf 1024 timer a timer b serial i/o a-d converter watchdog timer pins internal peripheral devices state in stop mode operation after terminating stop mode supply of f cpu and f biu starts after a certain time measured by watchdog timer has passed. operates in the same way as hardware reset
7751 group users manual stop mode 10C4 10.2.1 termination by interrupt request occurrence when terminating stop mode by interrupt request occurrence, instructions are executed after a certain time measured by the watchdog timer has passed. when an interrupt request occurs, the oscillator starts oscillating. simultaneously, supply of , clock f 1 , f 2 /f 4 to f 512 /f 1024 , wf 32 /wf 64 , and wf 512 /wf 1024 starts. the watchdog timer starts counting owing to the oscillation start. the watchdog timer counts wf 32 /wf 64 . a when the watchdog timers msb becomes 0, supply of f cpu , f biu starts. at the same time, the watchdog timers count source returns to wf 32 /wf 64 or wf 512 /wf 1024 that is selected by the watchdog timer frequency select bit (bit 0 at address 61 16 ). ? the interrupt request which occurs in is accepted. table 10.2.2 lists the interrupts used to terminate stop mode. table 10.2.2 interrupts used to terminate stop mode conditions for using each function to generate interrupt request interrupt ____ int i interrupt (i = 0 to 2) timer ai interrupt (i = 0 to 4) timer bi interrupt (i = 0 to 2) uarti transmit interrupt (i = 0, 1) uarti receive interrupt (i = 0, 1) 10.2 operation description enabled in event counter mode enabled when selecting external clock notes 1: since the oscillator has stopped oscillating, each function does not work unless they are operated under the above condition. also, the a-d converter does not work. 2: since the oscillator has stopped oscillating, no interrupts other than those above can be used. 3: refer to chapter 4. interrupt and the description of each internal peripheral device for details about each interrupt. before executing the stp instruction, enable interrupts used to terminate stop mode. in addition, the interrupt priority level of the interrupt used to terminate stop mode must be higher than the processor interrupt priority level (ipl) of the routine where the stp instruction is executed. when multiple interrupts in table 10.2.2 are enabled, stop mode is terminated by the first interrupt request. there is possibility that all interrupt requests occur after the oscillation starts in and until supply of cpu and biu starts in a . the interrupt requests which occur during this time are accepted in order of priority (note) after the watchdog timers msb becomes 0. for interrupts not to be accepted, set their interrupt priority levels to level 0 (interrupt disabled) before executing the stp instruction. note : the interrupt request which has the highest priority is accepted first. f f f
stop mode 7751 group users manual 10C5 fig. 10.2.1 stop mode terminating sequence by interrupt request occurrence 10.2.2 termination by hardware reset ______ supply l level to the reset pin by using the external circuit until the oscillation of the oscillator is stabilized. the cpu and the sfr area are initialized in the same way as the system reset. however, the internal ram area retains the same contents as that before executing the stp instruction. the termination sequence is the same as the internal processing sequence which is performed after a reset. to determine whether a hardware reset was performed to terminate stop mode or a system reset was performed, use software after a reset. refer to chapter 13. reset for details about a reset. 10.2 operation description cpu 1 0 . . . . . . . 7ff 16 fff 16 stop mode f(x in ) operating stopped stopped internal peripheral devices operating value of watchdog timer wf 32 /wf 64 5 2048 counts interrupt request used to terminate stop mode (interrupt request bit) stopped operating operating operating l interrupt request used to terminate stop mode occurs. l oscillation starts.(when an external clock is input from the x in pin, clock input starts.) l watchdog timer starts counting. l stp instruction is executed l watchdog timers msb = 0 (however, watchdog timer interrupt request does not occur.) l supply of cpu , biu starts. l interrupt request which has been used to terminate stop mode is accepted. cpu , biu
7751 group users manual stop mode 10C6 10.3 precautions for stop mode 1. when using the stp instruction with the mask rom version, select stp instruction enable with the stp instruction option on the mask rom order confirmation form. the stp instruction is always enabled in the built-in prom version and the flash memory version. 2. when executing the stp instruction after writing to the internal area or an external area, the three nop instructions must be inserted to complete the write operation before the stp instruction is executed. sta nop nop nop stp a, 5555 ; ; ; ; ; writing instruction nop instruction insertion stp instruction fig. 10.3.1 nop instruction insertion example 10.3 precautions for stop mode
chapter 11 wait mode 11.1 clock generating circuit 11.2 operation description 11.3 precautions for wait mode
7751 group users manual wait mode 11C2 this chapter describes wait mode. wait mode is used to stop cpu and biu when there is no need to operate the central processing unit (cpu). the microcomputer enters wait mode when the wit instruction is executed. wait mode can be terminated by an interrupt request occurrence or the hardware reset. 11.1 clock generating circuit figure 11.1.1 shows the clock generating circuit. 11.1 clock generating circuit fig. 11.1.1 clock generating circuit q x in x out r s q r s q r s 1 biu cpu 1/8 f 2 /f 4 1/4 1/8 f 16 /f 32 f 64 /f 128 f 512 /f 1024 wf 512 /wf 1024 interrupt request stp instruction reset wit instruction ready request request of cpu wait from biu operation clock for internal peripheral devices watchdog timer watchdog timer frequency select bit 1/2 1/2 0 1 hold request 1/16 1/16 wf 32 /wf 64 1 0 clock source for peripheral devices select bit clock source for peripheral devices select bit : bit 2 at address 5f 16 watchdog timer frequency select bit : bit 0 at address 61 16 cpu : central processing unit biu : bus interface unit note : this is the signal generated when the watchdog timers most significant bit becomes 0. (note)
wait mode 7751 group users manual 11C3 11.2 operation description 11.2 operation description when the wit instruction is executed, cpu and biu stop. the oscillators oscillation is not stopped. this state is called wait mode. in wait mode, the microcomputers power consumption is reduced though the vcc, power source voltage, is maintained. table 11.2.1 lists the microcomputer state and operation in and after wait mode. table 11.2.1 microcomputer state and operation in and after wait mode state and operation item operating stopped operating operating retains the same state in which the wit instruction was executed oscillation cpu , biu clock , 1 , f 2 /f 4 to f 512 /f 1024 , wf 32 /wf 64 , wf 512 /wf 1024 timer a timer b serial i/o a-d converter watchdog timer pins by interrupt request occurrence by hardware reset state in wait mode operation after termi- nating wait mode internal peripheral devices supply of cpu and biu starts just after the termination. operates in the same way as hardware reset
7751 group users manual wait mode 11C4 11.2.1 termination by interrupt request occurrence when an interrupt request occurs, supply of clock cpu and biu starts. the interrupt request which occurs in is accepted. table 11.2.2 shows the interrupts used to terminate wait mode. the occurrence of the watchdog timer interrupt request also terminates wait mode. before executing the wit instruction, enable interrupts used to terminate wait mode. in addition, the interrupt priority level of the interrupt used to terminate wait mode must be higher than the processor interrupt priority level (ipl) of the routine where the wit instruction is executed. when the multiple interrupts in table 11.2.2 are enabled, wait mode is terminated by the first interrupt request. 11.2.2 termination by hardware reset the cpu and the sfr area are initialized in the same way as a system reset. however, the internal ram area retains the same contents as that before executing the wit instruction. the termination sequence is the same as the internal processing sequence which is performed after a reset. to determine whether a hardware reset was performed to terminate wait mode or a system reset was performed, use software after a reset. refer to chapter 13. reset for details about a reset. 11.2 operation description table 11.2.2 interrupts used to terminate wait mode interrupt ____ ?int i interrupt (i = 0 to 2) ?timer ai interrupt (i = 0 to 4) ?timer bi interrupt (i = 0 to 2) ?uarti transmit interrupt (i = 0, 1) ?uarti receive interrupt (i = 0, 1) ?a-d converter interrupt note : refer to chapter 4. interrupts and each functional description about interrupts.
wait mode 7751 group users manual 11C5 11.3 precautions for wait mode when executing the wit instruction after writing to the internal area or an external area, the three nop instructions must be inserted to complete the write operation before the wit instruction is executed. 11.3 precautions for wait mode sta nop nop nop wit a, 5555 ; ; ; ; ; writing instruction nop instruction insertion wit instruction fig. 11.3.1 nop instruction insertion example
7751 group users manual wait mode 11C6 11.3 precautions for wait mode memorandum
chapter 12 connection with external devices 12.1 signals required for accessing external devices 12.2 bus cycle 12.3 ready function 12.4 hold function
connection with external devices 12.1 signals required for accessing external devices 7751 group users manual 12C2 this chapter describes functions to connect devices externally. 12.1 signals required for accessing external devices the functions and operation of the signals which are required for accessing external devices are described below. when connecting an external device that requires a long access time, refer to sections 12.2 bus cycle, 12.3 ready function, and 12.4 hold function, as well as this section. 12.1.1 descriptions of signals when an external device is connected, operate the microcomputer in the memory expansion or microprocessor _ mode. (refer to section 2.5 processor modes. ) in these modes, pins p0 to p4 and the e pin function as i/o pins for the signals required for accessing external devices. figure 12.1.1 shows the pin configuration in the memory expansion and microprocessor modes. table _ 12.1.1 lists the functions of pins p0 to p4 and the e pin in the memory expansion and the microprocessor modes.
connection with external devices 7751 group users manual 12C3 12.1 signals required for accessing external devices rdy a 20 /d 4 a 21 /d 5 a 22 /d 6 a 23 /d 7 r/w bhe ale hlda v ss e x out x in reset cnv ss byte hold p8 4 /cts 1 /rts 1 p8 5 /clk 1 p8 6 /r x d 1 p8 7 /t x d 1 a 0 a 1 a 2 a 3 a 4 a 5 a 6 a 7 a 8 /d 8 a 9 /d 9 a 10 /d 10 a 11 /d 11 a 12 /d 12 a 13 /d 13 a 14 /d 14 a 15 /d 15 a 16 /d 0 a 17 /d 1 a 18 /d 2 a 19 /d 3 p7 0 /an 0 p6 7 /tb2 in p6 6 /tb1 in p6 5 /tb0 in p6 4 /int 2 p6 3 /int 1 p6 2 /int 0 p6 1 /ta4 in p6 0 /ta4 out p5 7 /ta3 in p5 6 /ta3 out p5 5 /ta2 in p5 4 /ta2 out p5 3 /ta1 in p5 2 /ta1 out p5 1 /ta0 in p5 0 /ta0 out 25 27 26 28 34 29 30 31 32 33 35 36 37 38 39 40 14 3 25 p8 3 /t x d 0 p8 2 /r x d 0 p8 1 /clk 0 p8 0 /cts 0 /rts 0 v cc av cc v ref av ss v ss p7 7 /an 7 /ad trg p7 6 /an 6 p7 5 /an 5 p7 4 /an 4 p7 3 /an 3 p7 2 /an 2 p7 1 /an 1 6 7 8 9 101112131415161718192021 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 80 79 78 77 76 75 74 73 72 71 69 68 67 66 65 70 43 42 41 m37751m6c-xxxfp 22 23 24 p4 7 p4 6 p4 5 p4 4 p4 3 p4 2 / 1 l external data bus width = 16 bits (byte = l) ] : as 1 in microprocessor mode : external address bus, external data bus, bus control signal rdy a 20 /d 4 a 21 /d 5 a 22 /d 6 a 23 /d 7 r/w bhe ale hlda v ss e x out x in reset cnv ss byte hold a 11 a 12 a 13 a 14 a 15 a 16 /d 0 a 17 /d 1 a 18 /d 2 a 19 /d 3 p8 4 /cts 1 /rts 1 p8 5 /clk 1 p8 6 /r x d 1 p8 7 /t x d 1 a 0 a 1 a 2 a 3 a 4 a 5 a 6 a 7 a 8 a 9 a 10 14 3 2 56789101112131415161718192021222324 p7 0 /an 0 p6 7 /tb2 in p6 6 /tb1 in p6 5 /tb0 in p6 4 /int 2 p6 3 /int 1 p6 2 /int 0 p6 1 /ta4 in p6 0 /ta4 out p5 7 /ta3 in p5 6 /ta3 out p5 5 /ta2 in p5 4 /ta2 out p5 3 /ta1 in p5 2 /ta1 out p5 1 /ta0 in p5 0 /ta0 out 25 27 26 28 34 29 30 31 32 33 35 36 37 38 39 40 p8 3 /t x d 0 p8 2 /r x d 0 p8 1 /clk 0 p8 0 /cts 0 /rts 0 v cc av cc v ref av ss v ss p7 7 /an 7 /ad trg p7 6 /an 6 p7 5 /an 5 p7 4 /an 4 p7 3 /an 3 p7 2 /an 2 p7 1 /an 1 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 80 79 78 77 76 75 74 73 72 71 69 68 67 66 65 70 43 42 41 m37751m6c-xxxfp p4 7 p4 6 p4 5 p4 4 p4 3 p4 2 / 1 l external data bus width = 8 bits (byte = h) ] : as 1 in microprocessor mode : external address bus, external data bus, bus control signal fig. 12.1.1 pin configuration in memory expansion and microprocessor modes (top view) ] ]
connection with external devices 12.1 signals required for accessing external devices 7751 group users manual 12C4 _ table 12.1.1 functions of pins p0 to p4 and e pin in memory expansion and microprocessor modes notes 1 : in the memory expansion mode, this pin functions as a programmable i/o port and can be programmed as the clock 1 output pin by software. 2 : this table shows the pins functions. refer to the following about the input/output timing of each signal: 12.1.2 operation of bus interface unit (biu) ; 12.2 bus cycle ; 12.3 ready function ; 12.4 hold function chapter 15. electrical characteristics . hlda bhe ale r/w hlda d p rdy 1 hold e e pin external data bus width 16 bits (byte = l) a 7 to a 0 (p0) a 7 a 0 a 7 a 0 8 bits (byte = h) a 15 /d 15 to a 8 /d 8 (p1) a 23 /d 7 to a 16 /d 0 (p2) ale (p3 2 ) bhe (p3 1 ) r/w (p3 0 ) d(odd): data at odd address d(odd) a 15 a 8 a 15 /d 15 a 8 /d 8 a 15 a 8 a 15 a 8 a 23 /d 7 a 16 /d 0 a 23 a 16 d(even): data at even address d(even) a 23 /d 7 a 16 /d 0 a 23 a 16 d: data 1 (p4 2 ) p4 7 to p4 3 rdy (p4 1 ) hold (p4 0 ) p4 7 p4 3 p: functions as a programmable i/o port. (note 1) hlda (p3 3 ) ale bhe r/w 1 hold rdy e ;
connection with external devices 7751 group users manual 12C5 12.1 signals required for accessing external devices (1) external bus (a 0 to a 7 , a 8 /d 8 to a 15 /d 15 , a 16 /d 0 to a 23 /d 7 ) external areas are specified by the address (a 0 to a 23 ) output. figure 12.1.2 shows the external area. pins a 8 to a 23 of the external address bus and pins d 0 to d 15 of the external data bus are assigned to the same pins. when the byte pin level, described later, is l (i.e., external data bus width is 16 bits), the a 8 /d 8 to a 15 /d 15 and a 16 /d 0 to a 23 /d 7 pins perform address output and data input/output with time-sharing. when the byte pin level is h (i.e., external data bus width is 8 bits), the a 16 /d 0 to a 23 /d 7 pins perform address output and data input/output with time-sharing, and pins a 8 to a 15 output addresses. : external area note: addresses 2 16 to 9 16 become an external area. internal ram area sfr area ( note ) ffffff 16 microprocessor mode 000000 16 memory expansion mode 010000 16 ffffff 16 000080 16 internal rom area internal ram area sfr area ( note ) 004000 16 000880 16 000000 16 000080 16 000880 16 fig. 12.1.2 external area
connection with external devices 12.1 signals required for accessing external devices 7751 group user?s manual 12e6 (2) external data bus width switching signal (byte pin level) this signal is used to select the external data bus width be tween 8 bits and 16 bits. when this signal level is l, the external data bus width is 16 bits; when t he level is h, the bus width is 8 bits (refer to table 12.1.1.) f ix this signal to either h or l level. this signal is valid only for the external areas. when acces sing the internal areas, the data bus width is always 16 bits. (3) __ enable signal (e) this signal becomes l level while reading or writing data to and from the data bus. (see table 12.1.2.) (4) __ read/write signal ( r/w) this signal indicates the state of the data bus. this signal becomes l level while writing to the data __ _ bus. table 12.1.2 lists the state of the data bus indicated with the e and r/w signals. _ table 12.1.2 state of data bus indicated with e __ and r/w signals __ r/w h l h l _ e h l state of data bus not used read data write data (5) ____ byte high enable signal ( bhe) this signal indicates the access to an odd address. this sig nal becomes l level when accessing an only odd address or when simultaneously accessing odd and even addresses. this signal is used to connect memories or i/o devices of wh ich data bus width is 8 bits when the external data bus width is 16 bits. ____ table 12.1.3 lists levels of the external address bus a 0 and the bhe signal and access addresses. ____ table 12.1.3 levels of a 0 and bhe signal and access addresses access address a 0 ____ bhe even and odd addresses (simultaneous 2-byte access) l l even address (1-byte access) l h odd address (1-byte access) h l (6) address latch enable signal (ale) this signal is used to obtain the address from the multiplex ed signal of address and data that is input and output to and from the a 8 /d 8 to a 15 /d 15 and a 16 /d 0 to a 23 /d 7 pins. make sure that when this signal is h, latch the address and simultaneously output the addr esses. when this signal is l, retain the latched address. (7) ____ ready function-related signal ( rdy ) this is the signal to use the ready function. (refer to sect ion 12.3 ready function. ) (8) _____ _____ hold function-related signals ( hold , hlda ) these are the signals to use the hold function. (refer to se ction 12.4 hold function. )
connection with external devices 7751 group users manual 12C7 12.1 signals required for accessing external devices (9) clock f 1 this signal has the same period as f . in the memory expansion mode, this signal is output externally by setting the clock f 1 output select bit (bit 7 at address 5e 16 ) to 1. figure 12.1.3 shows the output start timing of clock f 1. in the microprocessor mode, this signal is always output externally. note: even in the single-chip mode, the clock f 1 can be output externally. this signal is output externally by setting the clock f 1 output select bit to 1 just as in the memory expansion mode. fig. 12.1.3 output start timing of clock f 1 fig. 12.1.4 structure of processor mode register bit bit name functions at reset rw 0 1 2 3 4 5 6 7 processor mode bits software reset bit interrupt priority detection time select bits clock 1 output select bit (note 2) 0 0 0 0 0 0 : single-chip mode 0 1 : memory expansion mode 1 0 : microprocessor mode 1 1 : not selected the microcomputer is reset by writing 1 to this bit. the value is 0 at reading. 0 0 : 7 cycles of 0 1 : 4 cycles of 1 0 : 2 cycles of 1 1 : not selected 0 : clock 1 output disabled (p4 2 functions as a programmable i/o port.) 1 : clock 1 output enabled (p4 2 functions as a clock 1 out- put pin.) 0 0 b1 b0 b5 b4 processor mode register 0 (address 5e 16 ) (note 1) notes 1: while supplying the vcc level to the cnvss pin, this bit becomes 1. (fixed to 1.) 2: this bit is ignored in the microprocessor mode. (it may be either 0 or 1.) b1 b0 b2 b3 b4 b5 b6 b7 0 rw rw fix this bit to 0. rw wo 0 rw 0 rw fix this bit to 0. rw rw 0 : bits 0 to 6 are not used for setting of clock 1 output. writing 1 to clock 1 output select bit e clock 1 (p4 2 ) notes 1 : the 1st cycle of clock 1 may be shortened; indicated by . 2 : this applies when writing to clock 1 output select bit while p4 2 pin is outputting l level.
connection with external devices 12.1 signals required for accessing external devices 7751 group users manual 12C8 12.1.2 operation of bus interface unit (biu) figures 12.1.5 and 12.1.6 show the examples of operating waveforms of the signals input and output to /from externals when accessing external devices. the following explains these waveforms compared with the basic operating waveform (refer to section 2.2.3 operation of bus interface unit (biu). ) (1) when fetching instructions into instruction queue buffer when the instruction which is next fetched is located at an even address in the 16-bit external data bus width, the biu fetches 2 bytes at a time with the waveform (a). when in the 8-bit external data bus width, the biu fetches only 1 byte with the first half of waveform (e). when the instruction which is next fetched is located at an odd address in the 16-bit external data bus width, the biu fetches only 1 byte with the waveform (d). when in the 8-bit external data bus width, the biu fetches only 1 byte with the first half of waveform (f). when a branch to an odd address is caused by a branch instruction and others in the 16-bit external data bus width, the biu first fetches 1 byte in waveform (d), and after that, fetches each two bytes at a time in waveform (a). (2) when reading or writing data to and from memory?i/o device when accessing 16-bit data which begins at an even address, waveform (a) or (e) is applied. when accessing 16-bit data which begins at an odd address, waveform (b) or (f) is applied. a when accessing 8-bit data at an even address, waveform (c) or the first half of (e) is applied. ? when accessing 8-bit data at an odd address, waveform (d) or the first half of (f) is applied. for instructions that are affected by the data length flag (m) and the index register length flag (x), operation or is applied when flag m or x = 0; operation a or ? is applied when flag m or x = 1. the setup of flags m and x and the selection of the external data bus width do not affect each other.
connection with external devices 7751 group users manual 12C9 12.1 signals required for accessing external devices a 0 to a 7 a 16 /d 0 to a 23 /d 7 e ale bhe a 0 a 8 /d 8 to a 15 /d 15 a 0 to a 7 a 16 /d 0 to a 23 /d 7 e ale bhe a 0 a 8 /d 8 to a 15 /d 15 a 0 to a 7 a 8 /d 8 to a 15 /d 15 bhe e a 0 ale a 16 /d 0 to a 23 /d 7 a 0 to a 7 a 8 /d 8 to a 15 /d 15 bhe e a 0 ale a 16 /d 0 to a 23 /d 7 (a) access from even address <16-bit data access> l external data bus width = 16 bits (byte = ?? address data(odd) data(even) address address (b) access from odd address address address address data(odd) address address address data(even) <8-bit data access> (c) access to even address address address data(even) address address (d) access to odd address data(odd) address address fig. 12.1.5 example of operating waveforms of signals input and output to/from externals (1)
connection with external devices 12.1 signals required for accessing external devices 7751 group users manual 12C10 e ale a 0 to a 7 bhe a 0 a 8 to a 15 a 16 /d 0 to a 23 /d 7 e ale a 0 to a 7 bhe a 0 a 8 to a 15 a 16 /d 0 to a 23 /d 7 l external data bus width = 8 bits (byte = ?? <8/16-bit data access> (e) access from even address address address data data 8-bit data access 16-bit data access address address address address data address data address address address address address 8-bit data access 16-bit data access (f) access from odd address note: when accessing 16-bit data, 2 times of access are performed in the sequence of the low-order 8 bits and high-order 8 bits. fig. 12.1.6 example of operating waveforms of signals input and output to/from externals (2)
connection with external devices 7751 group user's manual 12C11 12.2 bus cycle 12.2 bus cycle the bus cycle can be selected to make it easy to access the external devices which require a long access time. the bus cycle is selected with the bus cycle select bits (bits 4 and 5 at address 5f 16 ). the selectable bus cycle depends on the cpu running speed. the cpu running speed is selected with the cpu running speed select bit (bit 3 at address 5f 16 ). table 12.2.1 lists the selection of cpu running speed and bus cycle. figure 12.2.1 shows the structure of the processor mode register 1 (address 5f 16 ). table 12.2.2 lists each bus cycle. the selection of bus cycle is valid only for external areas. for the internal area, the access is performed with the fixed bus cycle. table 12.2.1 selection of cpu running speed and bus cycle access to internal area 2 f access in low-speed running high-speed running ram: 2 f access rom, sfr: 3 f access not selected access to external area ( note ) 2 f access in low-speed running 3 f access in low-speed running 4 f access in low-speed running 3 f access in high-speed running 4 f access in high-speed running 5 f access in high-speed running processor mode register 1 (address 5f 16 ) b5 b4 b3 111 101 011 100 010 000 110 001
connection with external devices 12.2 bus cycle 7751 group user's manual 12C12 b7 b6 b5 b4 b3 b2 b1 b0 processor mode register 1 (address 5f 16 ) bit 5 bus cycle select bits 3 2 1, 0 bit name at reset 0 rw functions in high-speed running 0 0 : 5 access in high-speed running 0 1 : 4 access in high-speed running 1 0 : 3 access in high-speed running 1 1 : not selected note: fix this bit to 0 when f(x in ) > 25 mhz. fix these bits to 0. 4 7, 6 rw rw rw rw 0 0 0 clock source for peripheral devices select bit (note) 0 : divided by 2 1 : cpu running speed select bit (note) 0 : high-speed running 1 : low-speed running rw 0 rw 0 b5 b4 in low-speed running 0 0 : not selected 0 1 : 4 access in low-speed running 1 0 : 3 access in low-speed running 1 1 : 2 access in low-speed running b5 b4 fix these bits to 0. 000 0 : bits 0 to 2, 6 and 7 are not used to select the bus cycle. fig. 12.2.1 structure of the processor mode register 1
connection with external devices 7751 group user's manual 12C13 12.2 bus cycle table 12.2.2 bus cycle 1 bus cycle = 2 2 access in high-speed running (ram) 1 bus cycle = 3 3 access in high-speed 1 bus cycle = 4 4 access in high-speed running 2 access in low-speed running 1 bus cycle = 2 2 access in low-speed running 1 bus cycle = 2 3 access in low-speed running 1 bus cycle = 3 4 access in low-speed running 1 bus cycle = 4 5 access in high-speed running 1 bus cycle = 5 1 bus cycle = 3 3 access in high-speed running (rom, sfr) ale reading writing n ote : signals when accessing an internal area means signals which are output from pins externally when accessing an internal area in the memory expansion mode. a : address w : data to be written r : data to be read ? : undefined value e high-speed running [ f (x in ) 40 mhz ] low-speed running [ f (x in ) 25 mhz ] internal area access external area access internal area access external area access (note) (note) a aw reading writing a aw r ale e reading writing a aw r ale e reading writing a w r e a reading writing a ? ale e a writing w ale e a a reading writing w ale e a a reading r writing w ale e a reading r a writing w ale e a reading r a writing w a reading r a writing w ale e a reading r a running
connection with external devices 12.3 ready function 7751 group users manual 12C14 12.3 ready function ready function provides the function to facilitate access to external devices that require a long access time. ____ by supplying l level to the rdy pin in the memory expansion or microprocessor mode, the microcomputer ____ enters ready state and retains this state while the rdy pin is at l level. table 12.3.1 lists the microcomputers state in ready state. in ready state, the oscillators oscillation does not stop, so that the internal peripheral devices can operate. ready function is valid for the internal and external areas. table 12.3.1 microcomputers state in ready state state operating stopped at l retains the state when ready request was accepted. in the memory expansion mode: ?when clock f 1 output select bit ] = 1, this pin outputs clock f 1 . ?when clock f 1 output select bit = 0, this pin retains the state when ready request was accepted. in the microprocessor mode: ?this pin outputs clock f 1 . operating item oscillation, f _ f cpu , f biu , e pins a 0 to a 7 , a 8 /d 8 to __ a 15 /d 15 , a 16 /d 0 to a 23 /d 7 , r/w, ____ _____ bhe, hlda, ale pins p4 3 to p4 7 , p5 to p8 (note) p4 2 / f 1 watchdog timer clock f 1 output select bit ] : bit 7 at address 5e 16 note: when this functions as a programmable i/o port.
connection with external devices 7751 group users manual 12C15 12.3 ready function 12.3.1 operation description ____ the input level of the rdy pin is judged at the last falling of the clock f 1 in each bus cycle. then, when l level is detected, the microcomputer enters ready state. (this is called acceptance of ready request.) ____ in ready state, the input level of the rdy pin is judged at every falling of the clock f 1 . then, when h level is detected, the microcomputer terminates ready state next rising of the clock f 1 . figures 12.3.1 and 12.3.2 show timing of acceptance of ready request and termination of ready state. refer also to section 17.1 memory expansion about usage of the ready function.
connection with external devices 12.3 ready function 7751 group users manual 12C16 fig. 12.3.1 timings of acceptance of ready request and termination of ready state (1) term unusing bus term using bus l 2 access in low-speed running, 2 access in high-speed running judgment timing of input level to rdy pin term using bus l 3 access in low-speed running, 3 access in high-speed running low-speed 3 clock 1 cpu rdy ale biu e cpu clock 1 rdy ale biu by accepting an ready request, l level of e signal stops for 1 cycle with the clock 1 , indicated by , and clocks biu and cpu stop at l level. ready state is terminated. ] input level to the rdy pin is not judged during the term unusing the bus or before the condition above . notes 1 : the timing of ale signal differs depending on low-speed running or high-speed running, and accessing an internal area or an external area. for more information, refer to section chapter 15. electrical characteristics . 2 : the dotted lines of signals biu , cpu and e indicate the waveform when input level to the rdy pin is h, no ready request. 3 : in high-speed running, the internal ram is accessed by 2 access in high-speed running. judgment timing of input level to rdy pin e high-speed 2 low-speed 2 high-speed 3
connection with external devices 7751 group users manual 12C17 12.3 ready function fig. 12.3.2 timings of acceptance of ready request and termination of ready state (2) term using bus l 4 access in low-speed running, 4 access in high-speed running term using bus l 5 access in high-speed running by accepting an ready request, l level of e signal stops for 1 cycle with the clock 1 , indicated by , and clocks biu and cpu stop at l level. ready state is terminated. ] input level to the rdy pin is not judged during the term unusing the bus or before the condition above . notes 1 : the timing of ale signal differs depending on low-speed running or high-speed running, and accessing an internal area or an external area. for more information, refer to section chapter 15. electrical characteristics . 2 : the dotted lines of signals biu , cpu and e indicate the waveform when input level to the rdy pin is h, no ready request. judgment timing of input level to rdy pin clock 1 cpu rdy ale biu e clock 1 cpu rdy ale biu e judgment timing of input level to rdy pin
connection with external devices 12.4 hold function 7751 group users manual 12C18 12.4 hold function when composing the external circuit (dma) which accesses the bus without using the central processing unit (cpu), the hold function is used to generate a timing for transferring the right to use the bus from the cpu to the external circuit. in the memory expansion or microprocessor mode, the microcomputer enters hold state by input of l level _____ _____ to the hold pin and retains this state while the level of the hold pin is at l. table 12.4.1 lists the microcomputers state in hold state. in hold state, the oscillation of the oscillator does not stop. accordingly, the internal peripheral devices can operate. however, watchdog timer stops operating. table 12.4.1 microcomputers state in hold state item oscillation f cpu f biu , f _ e pins a 0 to a 7 , a 8 /d 8 to a 15 /d 15 , __ ___ a 16 /d 0 to a 23 /d 7 , r/w, bhe _____ pins hlda, ale pin p4 2 / f 1 pins p4 3 to p4 7 , p5 to p8 (note) watchdog timer state operating stopped at l operating stopped at h floating outputs l level. in the memory expansion mode: ?when clock f 1 output select bit \ = 1, this pin outputs clock f 1 . ?when clock f 1 output select bit = 0, this pin retains the state when hold request was accepted. in the microprocessor mode: ?this pin outputs clock f 1 . retains the state when hold request was accepted. stopped clock f 1 output select bit \ : bit 7 at address 5e 16 note: when this functions as a programmable i/o port.
connection with external devices 7751 group users manual 12C19 12.4 hold function 12.4.1 operation description _____ judgment timing of the input level of the hold pin depends on the state using the bus. while the bus is not in use, the judgment is performed at every falling of f biu . while the bus is in use, the judgment timing _____ depends on the bus cycle. table 12.4.2 lists the judgment timing of the input level of the hold pin during the used bus. additionally, when accessing word data beginning from an odd address with 2-bus cycle, the judgment is performed only at the second bus cycle. (see figure 12.4.1.) when l level is detected at judgment of the input level, the microcomputer enters hold state. (this is called acceptance of hold request.) _____ when the hold request is accepted, f cpu stops next rising of f biu . at the same time, the hlda pins level _____ __ changes h to l. when 1 cycle of f biu has passed after the level of hlda pin becomes l, pins r/w, ___ bhe, and the external bus become floating state. _____ in hold state, the input level of the hold pin is judged at every falling of f biu . then, when h level is _____ detected, the hlda pins level changes l to h next rising of f biu . when 1 cycle of f biu has passed after _____ the level of hlda pin becomes h, the microcomputer terminates hold state. figures 12.4.2 to 12.4.4 show timing of acceptance of hold request and termination of hold state. note: f biu has a same polarity and a same frequency as the clock f 1 . however, f biu stops by acceptance of the ready request, or executing the stp or wit instruction. accordingly, judgment of the input _____ level of the hold pin is not performed during ready state. clock 1 biu ale reading writing judgment timing of input level to hold pin no judge judge accessing word data with 2-bus cycle. (example of 2 access in low-speed running ) e aa a w a w fig. 12.4.1 judgment when accessing word data beginning from odd address with 2-bus cycle
connection with external devices 12.4 hold function 7751 group users manual 12C20 _____ table 12.4.2 judgment timing of input level of hold pin during used bus 2 access in high-speed running (ram) 3 access in high-speed running 4 access in high-speed running 3 access in low-speed running 4 access in low-speed running 5 access in high-speed running 3 access in high-speed running n ote : signals when accessing an internal area means signals which are output from pins externally when accessing an internal area in the memory expansion mode. a : address w : data to be written r : data to be read ? : undefined value high-speed running [ f (x in ) 40 mhz ] low-speed running [ f (x in ) 25 mhz ] internal area access external area access internal area access external area access (note) (note) reading reading writing ale reading writing e a aw biu clock 1 2 access in low-speed running judgment timing of input level to hold pin 2 access in low-speed running judgment timing of input level to hold pin reading writing a aw r ale e biu clock 1 judgment timing of input level to hold pin writing a aw r ale e biu clock 1 judgment timing of input level to hold pin a w r e a biu clock 1 ale judgment timing of input level to hold pin reading writing a ? ale e a biu clock 1 judgment timing of input level to hold pin writing w ale e a a reading biu clock 1 judgment timing of input level to hold pin writing w ale e a a reading r biu clock 1 judgment timing of input level to hold pin writing w ale e a reading r a w a r a biu clock 1 judgment timing of input level to hold pin writing w a reading r a writing w ale e a reading r a biu clock 1 (rom, sfr)
connection with external devices 7751 group users manual 12C21 12.4 hold function external address bus bhe ale e hlda hold r/w clock 1 external data bus data length external data bus width 16 8, 16 unused l state when inputting l level to hold pin 8, 16 8 judgment timing of input level to hold pin ] external address bus / external data bus floating floating floating address a address b 1 5 1 hold state term using bus term unusing bus this is the term in which the bus is not used, so that not a new address but an address output just before is output again. ] clock 1 has the same polarity and the same frequency as biu . signals timing to be input or output externally is ordained by clock 1 as a basis. fig. 12.4.2 timing of acceptance of hold request and termination of hold state (1) 1 5 1
connection with external devices 12.4 hold function 7751 group users manual 12C22 fig. 12.4.3 timing of acceptance of hold request and termination of hold state (2) judgment timing of input level to hold pin external address bus bhe e hlda hold r/w 8 16 8, 16 16 (access from even address) l state when inputting l level to hold pin external data bus data length external data bus width using external address bus / external data bus ale clock 1 1 5 1 address b address a data floating floating address a floating hold state term using bus term using bus when accepting a hold request, not a new address but an address output just before is output again. notes 1: this figure shows the case of 2 access in low-speed running. 2: clock 1 has the same polarity and the same frequency as biu . signals timing to be input or output externally is ordained by clock 1 as a basis. 3 : this term indicated by note 3 becomes 1.5 cycles in 5 access in high-speed running. it is because the level judgment timing becomes the 1.5 cycles before the end of the term using bus (see table 12.4.2.) ] (note 3) 1 5 1
connection with external devices 7751 group users manual 12C23 12.4 hold function fig. 12.4.4 timing of acceptance of hold request and termination of hold state (3) address b e ale hlda hold r/w external address bus bhe 16 8 16 (access from odd address) using l state when inputting l level to hold pin external data bus data length external data bus width judgment timing of input level to hold pin clock 1 external address bus / external data bus address a+1 1 5 1 not accepted address a data data floating floating floating hold state term using bus term using bus when accepting a hold request, not a new address but an address output just before is output again. hold request cannot be accepted before input/output of 16-bit data is completed. notes 1 : this figure shows the case of 2 access in low-speed running. 2 : clock 1 has the same polarity and the same frequency as biu . signals timing to be input or output externally is ordained by clock 1 as a basis. 3 : this term indicated by note 3 becomes 1.5 cycles in 5 access in high-speed running. it is because the level judgment timing becomes the 1.5 cycles before the end of the term using bus (see table 12.4.2.) ] (note 3) 1 5 1
connection with external devices 12.4 hold function 7751 group users manual 12C24 memorandum
chapter 13 reset 13.1 hardware reset 13.2 software reset
reset 7751 group users manual 13C2 this chapter describes the method to reset the microcomputer. there are two methods to do that: hardware reset and software reset. 13.1 hardware reset when the power source voltage satisfies the microcomputers recommended operating conditions, the ______ microcomputer is reset by supplying l level to the reset pin. this is called a hardware reset. figure 13.1.1 shows an example of hardware reset timing. 13.1 hardware reset fig. 13.1.1 example of hardware reset timing the following explains how the microcomputer operates for terms to ? above. ______ after supplying l level to the reset pin, the microcomputer initializes pins within a term of several ten ns. (refer to table 13.1.1.) ______ while the reset pin is l level and within the term of 4 to 5 cycles of the internal clock f after the ______ reset pin goes from l to h, the microcomputer initializes the central processing unit (cpu) and sfr area. at this time, the contents of the internal ram area become undefined (except when stop or wait mode is terminated). (refer to figures 13.1.2 to 13.1.6.) a after , the microcomputer performs internal processing sequence after reset. (refer to figure 13.1.7.) ? the microcomputer executes a program beginning with the address set into the reset vector addresses which are fffe 16 and ffff 16 . reset program is executed. a? h 2 s or more internal processing sequence after a reset note: when the clock is stably supplied. (refer to 13.1.4 time supplying l level to reset pin. ) 4 to 5 cycles of l f
7751 group users manual reset 13C3 13.1 hardware reset 13.1.1 pin state ______ table 13.1.1 lists the microcomputers pin state while the reset pin is l level. ______ table 13.1.1 pin state while reset pin is l level mask rom version prom version (including one time prom and eprom versions) pin state floating. outputs h level. floating. outputs h level. floating. floating while supplying h level to two pins of p5 1 and p5 2 , or one of them. outputs h or l level while sup- plying l level to two pins of p5 1 and p5 2 . outputs h level. floating. outputs h level. floating. floating while supplying h level to two pins of p5 1 and p5 2 , or one of them. outputs h or l level while sup- plying l level to two pins of p5 1 and p5 2 . outputs h level. floating. pin (port) name p0 to p8 _ e p0 to p8 _ e p0, p1, p3 to p8 p2 cnv ss pin level vss or vcc vss vcc ( note 1 ) _ e p0 to p8 _ e p0, p1, p3 to p8 p2 flash memory version vss vcc ( note 2 ) _ e p0, p1, p3, p4 0 , p4 1 , p4 3 ,p4 5 to p4 7 , p5 to p8 p2 v pp h ( note 2 ) floating while supplying h level to two pins of p5 1 and p5 2 , or one of them. outputs h or l level while sup- plying l level to two pins of p5 1 and p5 2 . outputs clock f 1 . floating while supplying l level to one or more pins of p4 5 , p4 6 and p5 1 . outputs h or l level while sup- plying h level to three pins of p4 5 , p4 6 and p5 1 . outputs h level. p4 2 p4 4 _ e notes 1: each pin becomes the above state. it is because the microcomputer enters the eprom mode. refer to chapter 18. prom version . 2: each pin becomes the above state. it is because the microcomputer enters the flash memory mode. refer to chapter 19. flash memory version .
reset 7751 group users manual 13C4 13.1 hardware reset 13.1.2 state of cpu, sfr area, and internal ram area figure 13.1.2 shows the state of the cpu registers immediately after reset. figures 13.1.3 to 13.1.6 show the state of the sfr area and internal ram areas immediately after reset. fig. 13.1.2 state of cpu registers immediately after reset 0 : 0 immediately after a reset. 1 : 1 immediately after a reset. ? : undefined immediately after a reset. data bank register (dt) 00 16 b7 b0 program bank register (pg) 00 16 b7 b0 program counter (pc) contents at address fffe 16 contents at address ffff 16 b7 b0 b15 b8 direct page register (dpr) 00 16 b7 b0 00 16 b15 b8 processor status register (ps) 0 00 00 0 1 b7 b0 b15 b8 n v mxd izc ipl ? stack pointer (s) ? b7 b0 ? b15 b8 index register y (y) ? b7 b0 ? b15 b8 index register x (x) ? b7 b0 ? b15 b8 accumulator b (b) ? b7 b0 ? b15 b8 accumulator a (a) ? b7 b0 ? b15 b8 register name state immediately after a reset ??? : 0 immediately after a reset. fix to 0. (do not write 1 into this. 00000 0
7751 group users manual reset 13C5 13.1 hardware reset fig. 13.1.3 state of sfr and internal ram areas immediately after reset (1) 0 : 0 immediately after a reset. 1 : 1 immediately after a reset. ? : undefined immediately after a reset. : always 0 at reading. 0 0 : always undefined at reading. : 0 immediately after a reset. fix to 0. (do not write 1 into this.) 10 16 11 16 12 16 13 16 port p8 direction register 14 16 15 16 16 16 17 16 18 16 19 16 1a 16 1b 16 1c 16 1d 16 1e 16 1f 16 0 16 1 16 2 16 3 16 4 16 5 16 6 16 7 16 8 16 9 16 b 16 c 16 d 16 e 16 f 16 a 16 address port p4 register port p5 register port p4 direction register port p5 direction register port p6 register port p7 register port p6 direction register port p7 direction register port p8 register a-d control register 0 port p0 register port p1 register port p2 register port p3 register port p0 direction register port p1 direction register port p2 direction register port p3 direction register register name access characteristics state immediately after a reset rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw 00 16 00 16 ? 00 16 00 16 00 16 0000 00000000 00 16 00000 ? 11 b7 b0 b7 b0 : it is possible to read the bit state at reading. the written value becomes valid data. : it is possible to read the bit state at reading. the written value becomes invalid. : the written value becomes valid data. it is not possible to read the bit state. : nothing is assigned. it is not possible to read the bit state. the written value becomes invalid. rw ro wo l sfr area (0 16 to 7f 16 ) rw rw rw ? ? ? ? ? ? ? ? ? ? ? ? ? ? 00 16 ? ? ? @ 0 00 16 ? ? ? ? ? ? ? ? ? a-d control register 1 000
reset 7751 group users manual 13C6 13.1 hardware reset fig. 13.1.4 state of sfr and internal ram areas immediately after reset (2) uart0 transmit/receive control register 0 uart0 transmit/receive mode register uart0 baud rate register uart0 transmit buffer register uart1 receive buffer register register name uart0 transmit/receive control register 1 uart0 receive buffer register uart1 transmit/receive mode register uart1 baud rate register uart1 transmit buffer register uart1 transmit/receive control register 0 uart1 transmit/receive control register 1 30 16 31 16 32 16 33 16 34 16 35 16 36 16 37 16 38 16 39 16 3a 16 3b 16 3c 16 3d 16 3e 16 28 16 29 16 2b 16 2c 16 2d 16 2e 16 2f 16 2a 16 20 16 21 16 22 16 23 16 24 16 25 16 26 16 27 16 3f 16 address access characteristics rw wo wo ro ro b7 b0 wo rw ro ro ro rw rw ro ro rw wo wo wo rw ro rw rw state immediately after a reset 1000 00 16 0 000 00 0 ? b7 b0 00 16 00000010 0000 0 00 1000 0000 0 0 1 0 ? ? ? ? ? ? ? ? ? ? a-d register 5 a-d register 1 a-d register 3 a-d register 2 a-d register 4 a-d register 0 a-d register 6 a-d register 7 ro ro ro ro ro ro ro ro ro ro ? ? ? ? ? ? ? ??? ??? ro ro ro ro ro ro ro ro ? 000 00 0 ? 000 00 0 ? 000 00 0 ? 000 00 0 ? 000 00 0 ? 000 00 0 ? 000 00 0 ? 000 00 0 rw 0 rw 0
7751 group users manual reset 13C7 13.1 hardware reset fig. 13.1.5 state of sfr and internal ram areas immediately after reset (3) rw rw rw timer b2 register 40 16 41 16 42 16 43 16 44 16 45 16 46 16 47 16 48 16 49 16 50 16 51 16 52 16 53 16 54 16 55 16 56 16 57 16 58 16 59 16 5a 16 5b 16 5c 16 5d 16 5e 16 5f 16 4b 16 4c 16 4d 16 4e 16 4f 16 4a 16 address timer a2 register timer a3 register timer a4 register timer b0 register timer b1 register processor mode register 0 one-shot start register timer a0 register up-down register timer a1 register register name count start register timer a1 mode register timer a2 mode register timer a3 mode register timer b0 mode register timer b1 mode register timer b2 mode register access characteristics wo (note 1) (note 1) (note 1) (note 1) (note 1) (note 2) (note 2) (note 2) (note 2) b7 b0 rw (note 2) (note 2) rw rw rw rw rw rw wo state immediately after a reset 00 16 00 16 00 16 00 16 ? 00 16 b7 b0 00 16 wo rw (note 1) (note 1) (note 1) (note 1) (note 1) rw timer a0 mode register timer a4 mode register (note 3) 0 00 0 0 0 0 0 0 0 0 0 0 00 0 000 0 0 0 0 0 0 rw rw ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? (note 4) notes 1: the access characteristics at addresses 46 16 to 4f 16 vary according to timer as operating mode. (refer to chapter 5. timer a. ) 2: the access characteristics at addresses 50 16 to 55 16 vary according to timer bs operating mode. (refer to chapter 6. timer b. ) 3: the access characteristics for bit 5 at addresses 5b 16 to 5d 16 vary according to timer bs operating mode. (refer to chapter 6. timer b. ) 4: the access characteristics for bit 1 at address 5e 16 and its state immediately after a reset vary according to the voltage level supplied to the cnvss pin. (refer to section 2.5 processor modes. ) (note 4) rw (note 3) rw (note 3) 0 0 000 ? ? 00000 ? ? processor mode register 1 rw 0 0 0 0 0 00 00 0 0
reset 7751 group users manual 13C8 13.1 hardware reset fig. 13.1.6 state of sfr and internal ram areas immediately after reset (4) uart1 receive interrupt control register 60 16 61 16 62 16 63 16 64 16 65 16 66 16 67 16 68 16 69 16 70 16 71 16 72 16 73 16 74 16 75 16 76 16 77 16 78 16 79 16 7a 16 7b 16 7c 16 7d 16 7e 16 7f 16 6b 16 6c 16 6d 16 6e 16 6f 16 6a 16 address a-d conversion interrupt control register uart0 transmit interrupt control register uart1 transmit interrupt control register int 2 interrupt control register watchdog timer frequency select register register name watchdog timer register timer a0 interrupt control register timer a2 interrupt control register timer a3 interrupt control register timer a4 interrupt control register timer b1 interrupt control register timer b2 interrupt control register int 0 interrupt control register access characteristics rw b7 b0 rw state immediately after a reset 0 ? (note 2) b7 b0 uart0 receive interrupt control register timer a1 interrupt control register timer b0 interrupt control register int 1 interrupt control register 0 0 000 l internal ram area; addresses 80 16 to 87f 16 in m37751m6c-xxxfp) ?at hardware reset (except the case that stop or wait mode is terminated)............................................... undefined. ?at software reset.......................................................... retaining the state immediately before a reset ?at terminating stop or wait mode (hardware reset is used to terminate it)............... retaining the state immediately before the stp or wit instruction is executed rw notes 1: by writing dummy data to address 60 16 , a value fff 16 is set to the watchdog timer. the dummy data is not retained anywhere. 2: the value fff 16 is set to the watchdog timer. (refer to chapter 9. watchdog timer .) ? (note 3) ? ? ? rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw 0 000 ? 0 00 0 ? 0 00 0 ? 0 000 ? 0 000 ? 0 00 0 ? 0 00 0 ? 0 000 ? 0 000 ? 0 00 0 ? 0 00 0 ? 0 000 0 000 0 000 0 0 0 0 0 0 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 00 (note 1) ?
7751 group users manual reset 13C9 13.1.3 internal processing sequence after reset figure 13.1.7 shows the internal processing sequence after reset. 13.1 hardware reset (1) in single-chip and memory expansion modes (cnvss = vss) (2) in microprocessor mode (cnvss = vcc) cpu a h(cpu) a m a l(cpu) data (cpu) e 0000 16 00 16 fffe 16 ad m , ad l ad m , ad l 00 16 00 16 ale a 19 Ca 16 a 15 Ca 0 d 15 Cd 0 e ale 0000 16 0 16 fffe 16 ad m , ad l ad m , ad l 0 16 0 16 next op-code ipl, reset vector address undefined ipl, reset vector address undefined next op-code note : the only e signal is output externaly. note: the cpu signal is not output cpu 1 fig. 13.1.7 internal processing sequence after reset
reset 7751 group users manual 13C10 ______ 13.1.4 time supplying l level to reset pin ______ time supplying l level to the reset pin varies according to the state of the clock oscillation circuit. l when the oscillator is stably oscillating or a stable clock is input from the x in pin, supply l level for 2 s or more. l if the oscillator is not stably oscillating (including a power-on reset and in stop mode), supply l level until the oscillation is stabilized. the time to stabilize oscillation varies according to the oscillator. for details, contact the oscillator manufacturer. figure 13.1.8 shows the power-on reset condition. figure 13.1.9 shows an example of a power-on reset circuit. ] for details about stop mode, refer to chapter 10. stop mode. for details about clocks, refer to chapter 14. clock generating circuit. 13.1 hardware reset 0v 0v vcc reset powered on here 4.5v 0.9v fig. 13.1.8 power-on reset condition
7751 group users manual reset 13C11 13.1 hardware reset 1 in out gnd delay capacity reset vcc vss 47 sw c d gnd 3 25 5v m51957al m37751 27k 10k 4 ] the delay time is about 11 ms when c d = 0.033 m f. t d ? 0.34 5 c d [ m s], c d : [ pf ] vcc fig. 13.1.9 example of power-on reset circuit w w w
reset 7751 group users manual 13C12 13.2 software reset 13.2 software reset when the power source voltage satisfies the microcomputers recommended operating conditions, the microcomputer is reset by writing 1 to the software reset bit (bit 3 at address 5e 16 ). this is called a software reset. in this case, the microcomputer initializes pins, cpu, and sfr area just as in the case of a hardware reset. however, the microcomputer retains the contents of the internal ram area. (refer to table 13.1.1 and figures 13.1.2 to 13.1.6.) figure 13.2.1 shows the structure of processor mode register 0. after completing initialization, the microcomputer performs the internal processing sequence after a reset. (refer to figure 13.1.7.) after that, it executes a program beginning from the address set into the reset vector addresses which are fffe 16 and ffff 16. i bit bit name functions at reset rw 0 1 2 3 4 5 6 7 processor mode bits software reset bit interrupt priority detection time select bits clock 1 output select bit (note 2) 0 0 0 0 0 0 : single-chip mode 0 1 : memory expansion mode 1 0 : microprocessor mode 1 1 : not selected the microcomputer is reset by writing 1 to this bit. the value is 0 at reading. 0 0 : 7 cycles of 0 1 : 4 cycles of 1 0 : 2 cycles of 1 1 : not selected 0 : clock 1 output disabled (p4 2 functions as a programmable i/o port.) 1 : clock 1 output enabled (p4 2 functions as a clock 1 out- put pin.) 0 0 b1 b0 b5 b4 processor mode register 0 (address 5e 16 ) (note 1) notes 1: while supplying the vcc level to the cnvss pin, this bit becomes 1. (fixed to 1.) 2: this bit is ignored in the microprocessor mode. (it may be either 0 or 1.) b1 b0 b2 b3 b4 b5 b6 b7 0 rw rw fix this bit to 0. rw wo 0 rw 0 rw fix this bit to 0. rw rw 0 : bits 0 to 2, and bits 4 to 7 are not used for software reset. fig. 13.2.1 structure of processor mode register 0
chapter 14 clock generating circuit 14.1 oscillation circuit example 14.2 clock
clock generating circuit 7751 group users manual 14C2 this chapter describes a clock generating circuit which supplies the operating clock of the central processing unit (cpu), bus interface unit (biu), or internal peripheral devices. the clock generating circuit contains the oscillation circuit. 14.1 oscillation circuit example to the oscillation circuit, a ceramic resonator or a quartz-crystal oscillator can be connected, or the clock which is externally generated can be input. the example of the oscillation circuit is described below. 14.1.1 connection example using resonator/oscillator figure 14.1.1 shows an example when connecting a ceramic resonator/quartz-crystal oscillator between pins x in and x out . the circuit constants such as r f , r d , c in , and c out (shown in figure 14.1.1) depend on the resonator/ oscillator. these values shall be set to the resonator/ oscillator manufacturers recommended values. 14.1 oscillation circuit example fig. 14.1.1 connection example using resonator/oscillator fig. 14.1.2 externally generated clock input example 14.1.2 input example of externally generated clock figure 14.1.2 shows an input example of the clock which is externally generated. the external clock must be input from the x in pin, and the x out pin must be left open. m37751 x in x out r f c in c out r d m37751 externally generated clock open x in x out v cc v ss
clock generating circuit 14C3 7751 group users manual 14.2 clock 14.2 clock figure 14.2.1 shows the clock generating circuit block diagram. 1/8 1/4 f 2 /f 4 f 16 /f 32 f 64 /f 128 f 512 /f 1024 watchdog timer frequency select bit watchdog timer interrupt request wit instruction stp instruction reset s r q s r q s r q x in x out 1/2 1/2 0 1 ready request cpu biu hold request 1/8 1/16 wf 32 /wf 64 1 operation clock for internal peripheral devices request of cpu wait from biu clock source for peripheral devices select bit cpu : central processing unit biu : bus interface unit clock source for peripheral devices select bit: bit 2 at address 5f 16 watchdog timer frequency select bit : bit 0 at address 61 16 note: this is the signal generated when the watchdog timers most significant bit becomes 0. (note) 1 0 wf 512 /wf 1024 1/16 fig. 14.2.1 clock generating circuit block diagram
clock generating circuit 7751 group users manual 14C4 14.2.1 clock generated in clock generating circuit (1) f this is the clock source of f cpu , f biu clock f 1 , f 2 /f 4 to f 512 /f 1024 , wf 32 /wf 64 and wf 512 /wf 1024 . (2) f cpu this is the operation clock of cpu. (3) f biu this is the operation clock of biu. (4) clock f 1 this has the same period as f and is output to the external. 14.2 clock (5) f 2 /f 4 to f 512 /f 1024 each of them is the operation clock for the internal peripheral devices, and its clock source is f or f divided by 2. (refer to 14.2.2 operation clock for internal peripheral devices .) table 14.2.1 operation clock for internal peripheral devices operation clock clock source for peripheral devices select bit (see fig. 14.2.2) 10 f 2 /f 4 f 2 f 4 f 16 /f 32 f 16 f 32 f 64 /f 128 f 64 f 128 f 512 /f 1024 f 512 f 1024 (6) wf 32 /wf 64 , wf 512 /wf 1024 this is the operation clock of watchdog timer, and its clock source is f or f divided by 2. (refer to 14.2.2 operation clock for internal peripheral devices .) table 14.2.2 operation clock for watchdog timer operation clock clock source for peripheral devices select bit (see fig. 14.2.2) 10 wf 32 /wf 64 wf 32 wf 64 wf 512 /wf 1024 wf 512 wf 1024
clock generating circuit 14C5 7751 group users manual 14.2.2 operation clock for internal peripheral devices the operation clock for the internal peripheral devices uses f or f divided by 2 as its clock source. the clock source of the operation clock for internal peripheral devices is selected by the clock source for peripheral devices select bit (bit 2 at address 5f 16 ). figure 14.2.2 shows the structure of processor mode register 1 (address 5f 16 ). when f(x in ) > 25 mhz, fix the clock source for peripheral devices select bit to 0. 14.2 clock b7 b6 b5 b4 b3 b2 b1 b0 processor mode register 1 (address 5f 16 ) bit 5 bus cycle select bits 3 2 1, 0 bit name at reset 0 rw functions in high-speed running 0 0 : 5 access in high-speed running 0 1 : 4 access in high-speed running 1 0 : 3 access in high-speed running 1 1 : not selected note: fix this bit to 0 when f(x in ) > 25 mhz. fix these bits to 0. 4 7, 6 rw rw rw rw 0 0 0 clock source for peripheral devices select bit (note) 0 : divided by 2 1 : cpu running speed select bit (note) 0 : high-speed running 1 : low-speed running rw 0 rw 0 b5 b4 in low-speed running 0 0 : not selected 0 1 : 4 access in low-speed running 1 0 : 3 access in low-speed running 1 1 : 2 access in low-speed running b5 b4 fix these bits to 0. 000 0 : bits 0, 1, and bits 3 to 7 are not used for the clock generating circuit. fig. 14.2.2 structure of processor mode register 1
clock generating circuit 7751 group users manual 14C6 14.2 clock memorandum
chapter 15 electrical characteristics 15.1 absolute maximum ratings 15.2 recommended operating conditions 15.3 electrical characteristics 15.4 a-d converter characteristics 15.5 internal peripheral devices 15.6 ready and hold 15.7 single-chip mode 15.8 memory expansion mode and microprocessor mode : when 2- f access in low-speed running 15.9 memory expansion mode and microprocessor mode : when 3- f access in low-speed running 15.10 memory expansion mode and microprocessor mode : when 4- f access in low-speed running 15.11 memory expansion mode and microprocessor mode : when 3- f access in high-speed running 15.12 memory expansion mode and microprocessor mode : when 4- f access in high-speed running 15.13 memory expansion mode and microprocessor mode : when 5- f access in high-speed running 15.14 memory expansion mode and microprocessor mode : when 2- f access in high-speed running (internal ram access) 15.15 testing circuit for ports p0 to p8, _ f 1 , and e
electrical characteristics 7751 group users manual 15C2 15.1 absolute maximum ratings this chapter describes electrical characteristics of the m37751m6c-xxxfp. for the latest data, inquire of addresses described last ( + contact addresses for further information) . 15.1 absolute maximum ratings absolute maximum ratings parameter power source voltage analog power source voltage input voltage input voltage output voltage power dissipation operating temperature storage temperature conditions ta = 25 c ratings C0.3 to 7 C0.3 to 7 C0.3 to 12 C0.3 to v cc +0.3 C0.3 to v cc +0.3 300 C20 to 85 C40 to 150 unit v v v v v mw c c symbol v cc av cc v i v i v o p d t opr t stg ______ reset , cnv ss , byte p0 0 Cp0 7 , p1 0 Cp1 7 , p2 0 Cp2 7 , p3 0 Cp3 3 , p4 0 Cp4 7 , p5 0 Cp5 7 , p6 0 Cp6 7 , p7 0 Cp7 7 , p8 0 Cp8 7 , v ref , x in p0 0 Cp0 7 , p1 0 Cp1 7 , p2 0 Cp2 7 , p3 0 Cp3 3 , p4 0 Cp4 7 , p5 0 Cp5 7 , p6 0 Cp6 7 , p7 0 Cp7 7 , p8 0 Cp8 7 , _ x out , e
electrical characteristics 7751 group users manual 15C3 v v v v v v v v v v ma ma ma ma mhz power source voltage analog power source voltage power source voltage analog power source voltage high-level input voltage high-level input voltage high-level input voltage low-level input voltage low-level input voltage low-level input voltage high-level peak output current high-level average output current low-level peak output current low-level average output current operating clock frequency 15.2 recommended operating conditions recommended operating conditions (v cc = 5 v 10%, ta = C20 to 85 c, unless otherwise noted) 15.2 recommended operating conditions v cc av cc v ss av ss v ih v ih v ih v il v il v il i oh (peak) i oh (avg) i ol (peak) i ol (avg) f(x in ) parameter symbol limits min. max. 5.5 4.5 5.0 v cc 0 0 typ. unit v cc v cc v cc 0.2 v cc 0.2 v cc 0.16 v cc C10 C5 10 5 40 0.5 v cc 0 0 0 p0 0 Cp0 7 , p3 0 Cp3 3 , p4 0 Cp4 7 , p5 0 Cp5 7 , p6 0 Cp6 7 , p7 0 Cp7 7 , ______ p8 0 Cp8 7 , x in , reset , cnv ss , byte p1 0 Cp1 7 , p2 0 Cp2 7 (in single-chip mode) p1 0 Cp1 7 , p2 0 Cp2 7 (in memory expansion mode and microprocessor mode) p0 0 Cp0 7 , p3 0 Cp3 3 , p4 0 Cp4 7 , p5 0 Cp5 7 , p6 0 Cp6 7 , p7 0 Cp7 7 , ______ p8 0 Cp8 7 , x in , reset , cnv ss , byte p1 0 Cp1 7 , p2 0 Cp2 7 (in single-chip mode) p1 0 Cp1 7 , p2 0 Cp2 7 (in memory expansion mode and microprocessor mode) p0 0 Cp0 7 , p1 0 Cp1 7 , p2 0 Cp2 7 , p3 0 Cp3 3 , p4 0 Cp4 7 , p5 0 Cp5 7 , p6 0 Cp6 7 , p7 0 Cp7 7 , p8 0 Cp8 7 p0 0 Cp0 7 , p1 0 Cp1 7 , p2 0 Cp2 7 , p3 0 Cp3 3 , p4 0 Cp4 7 , p5 0 Cp5 7 , p6 0 Cp6 7 , p7 0 Cp7 7 , p8 0 Cp8 7 p0 0 Cp0 7 , p1 0 Cp1 7 , p2 0 Cp2 7 , p3 0 Cp3 3 , p4 0 Cp4 7 , p5 0 Cp5 7 , p6 0 Cp6 7 , p7 0 Cp7 7 , p8 0 Cp8 7 p0 0 Cp0 7 , p1 0 Cp1 7 , p2 0 Cp2 7 , p3 0 Cp3 3 , p4 0 Cp4 7 , p5 0 Cp5 7 , p6 0 Cp6 7 , p7 0 Cp7 7 , p8 0 Cp8 7 0.8 v cc 0.8 v cc notes 1: average output current is the average value of a 100 ms interval. 2: the sum of i ol (peak) for ports p0, p1, p2, p3, and p8 must be 80 ma or less, the sum of i oh (peak) for ports p0, p1, p2, p3, and p8 must be 80 ma or less, the sum of i ol (peak) for ports p4, p5, p6, and p7 must be 80 ma or less, and the sum of i oh (peak) for ports p4, p5, p6, and p7 must be 80 ma or less.
electrical characteristics 7751 group users manual 15C4 hold , rdy , ta0 in Cta4 in , tb0 in Ctb2 in , int 0 C int 2 , ad trg , cts 0 , cts 1 , clk 0 , clk 1 15.3 electrical characteristics electrical characteristics (v cc = 5 v, v ss = 0 v, ta = C20 to 85 c, f(x in ) = 40 mhz, unless otherwise noted) 15.3 electrical characteristics v oh v oh v oh v oh v ol v ol v ol v ol v t+ Cv tC v t+ Cv tC v t+ Cv tC i ih i il v ram i cc symbol parameter test conditions min. max. v v v v v v v v v v v m a m a v ma m a m a unit 3 4.7 3.1 4.8 3.4 4.8 0.4 0.2 0.1 2 2 0.45 1.9 0.43 1.6 0.4 1 0.5 0.3 5 C5 50 1 20 typ. 25 p0 0 Cp0 7 , p1 0 Cp1 7 , p2 0 Cp2 7 , p3 0 , p3 1 , p3 3 , p4 0 Cp4 7 , p5 0 Cp5 7 , p6 0 Cp6 7 , p7 0 Cp7 7 , p8 0 Cp8 7 p0 0 Cp0 7 , p1 0 Cp1 7 , p2 0 Cp2 7 , p3 0 , p3 1 , p3 3 p3 2 e p0 0 Cp0 7 , p1 0 Cp1 7 , p2 0 Cp2 7 , p3 0 , p3 1 , p3 3 , p4 0 Cp4 7 , p5 0 Cp5 7 , p6 0 Cp6 7 , p7 0 Cp7 7 , p8 0 Cp8 7 p0 0 Cp0 7 , p1 0 Cp1 7 , p2 0 Cp2 7 , p3 0 , p3 1 , p3 3 p3 2 e reset x in p0 0 Cp0 7 , p1 0 Cp1 7 , p2 0 Cp2 7 , p3 0 Cp3 3 , p4 0 Cp4 7 , p5 0 Cp5 7 , p6 0 Cp6 7 , p7 0 Cp7 7 , p8 0 Cp8 7 , x in , reset , cnv ss , byte p0 0 Cp0 7 , p1 0 Cp1 7 , p2 0 Cp2 7 , p3 0 Cp3 3 , p4 0 Cp4 7 , p5 0 Cp5 7 , p6 0 Cp6 7 , p7 0 Cp7 7 , p8 0 Cp8 7 , x in , reset , cnv ss , byte i oh = C10 ma i oh = C400 m a i oh = C10 ma i oh = C400 m a i oh = C10 ma i oh = C400 m a i ol = 10 ma i ol = 2 ma i ol = 10 ma i ol = 2 ma i ol = 10 ma i ol = 2 ma v i = 5 v v i = 0 v when clock is stopped. in single-chip mode, output pins are open, and the other pins are connected to v ss . f(x in ) = 40 mhz limits ta = 85c, when clock is stopped ta = 25c, when clock is stopped high-level output voltage high-level output voltage high-level output voltage high-level output voltage low-level output voltage low-level output voltage low-level output voltage low-level output voltage hysteresis hysteresis hysteresis high-level input current low-level input current ram hold voltage power source current
electrical characteristics 7751 group users manual 15C5 15.4 a-d converter characteristics 15.4 a-d converter characteristics a-d converter characteristics (v cc = av cc = 5 v 10%, v ss = av ss = 0 v, ta = C20 to 85 c, unless otherwise noted) unit r ladder t conv v ref v ia parameter resolution absolute accuracy ladder resistance conversion time reference voltage analog input voltage test conditions v ref = v cc v ref = v cc v ref = v cc f(x in ) = 40 mhz f(x in ) = 25 mhz limits min. 5 5.9 4.9 4.72 3.92 2 0 bits lsb k w s v v resolution 10 bit resolution 8 bit max. 10 3 2 v cc v ref typ. resolution 10 bit resolution 8 bit resolution 10 bit resolution 8 bit symbol
electrical characteristics 7751 group users manual 15C6 15.5 internal peripheral devices timing requirements (v cc = 5 v 10%, v ss = 0 v, ta = C20 to 85 c, unless otherwise noted) 15.5 internal peripheral devices limits t c(ta) t w(tah) t w(tal) tai in input cycle time tai in input high-level pulse width tai in input low-level pulse width min. 80 40 40 max. ns ns ns unit symbol parameter timer a input (count input in event counter mode) limits t c(ta) t w(tah) t w(tal) tai in input cycle time tai in input high-level pulse width tai in input low-level pulse width min. max. unit symbol parameter timer a input (gating input in timer mode) data formula (min.) f(x in ) 40 mhz f(x in ) 25 mhz when f divided by 2 selected as clock source for peripheral devices f(x in ) 25 mhz when f selected as clock source for peripheral devices 400 640 320 ns 16 5 10 9 f(x in ) 16 5 10 9 f(x in ) 8 5 10 9 f(x in ) f(x in ) 40 mhz f(x in ) 25 mhz when f divided by 2 selected as clock source for peripheral devices f(x in ) 25 mhz when f selected as clock source for peripheral devices 200 320 160 ns 8 5 10 9 f(x in ) 8 5 10 9 f(x in ) 4 5 10 9 f(x in ) f(x in ) 40 mhz f(x in ) 25 mhz when f divided by 2 selected as clock source for peripheral devices f(x in ) 25 mhz when f selected as clock source for peripheral devices 200 320 160 ns 8 5 10 9 f(x in ) 8 5 10 9 f(x in ) 4 5 10 9 f(x in ) notes 1: tai in input cycle time must be 4 cycles or more of count source, tai in input high-level pulse width must be 2 cycles or more of count source, tai in input low-level pulse width must be 2 cycles or more of count source. 2: the limits in the upper row of the table are the values when f(x in ) is 40 mhz and the count source is f 4 . the limits in the middle row of the table are the values when f(x in ) is 25 mhz and the count source is f 4 . the limits in the lower row of the table are the values when f(x in ) is 25 mhz and the count source is f 2 .
electrical characteristics 7751 group users manual 15C7 15.5 internal peripheral devices limits min. max. unit symbol parameter timer a input (external trigger input in one-shot pulse mode) data formula (min.) f(x in ) 40 mhz f(x in ) 25 mhz when f divided by 2 selected as clock source for peripheral devices f(x in ) 25 mhz when f selected as clock source for peripheral devices 8 5 10 9 f(x in ) 8 5 10 9 f(x in ) 4 5 10 9 f(x in ) tai in input cycle time ( note ) tai in input high-level pulse width tai in input low-level pulse width t c(ta) t w(tah) t w(tal) 200 320 160 80 80 ns ns ns limits min. 80 80 max. ns ns unit parameter timer a input (external trigger input in pulse width modulation mode) symbol tai in input high-level pulse width tai in input low-level pulse width limits min. 2000 1000 1000 400 400 max. ns ns ns ns ns unit parameter symbol timer a input (up-down input in event counter mode) t c(up) t w(uph) t w(upl) t su(upCt in ) t h(t in Cup) tai out input cycle time tai out input high-level pulse width tai out input low-level pulse width tai out input setup time tai out input hold time note: the limits in the upper row of the table are the values when f(x in ) is 40 mhz and the count source is f 4 . the limits in the middle row of the table are the values when f(x in ) is 25 mhz and the count source is f 4 . the limits in the lower row of the table are the values when f(x in ) is 25 mhz and the count source is f 2 . t w(tah) t w(tal) timer a input (two-phase pulse input in event counter mode) limits unit parameter symbol t su(taj in Ctaj out ) t su(taj out Ctaj in ) taj in input setup time taj out input setup time min. 200 200 max. ns ns
electrical characteristics 7751 group users manual 15C8 15.5 internal peripheral devices internal peripheral devices tai in input t c(ta) t w(tah) t w(tal) tai out input (up-down input) t c(up) t w(uph) t w(upl) tai in input (when fall count is selected) tai in input (when rise count is selected) tai out input (up-down input) t h(t in Cup) t su(upCt in ) l count input in event counter mode l gating input in timer mode l external trigger input in one-shot pulse mode l external trigger input in pulse width modulation mode l up-down input and count input in event counter mode test conditions ?v cc = 5 v10% ?input timing voltage : v il = 1.0 v, v ih = 4.0 v t su(taj in Ctaj out ) taj in input taj out input t su(taj out Ctaj in ) t su(taj in Ctaj out ) t su(taj out Ctaj in ) l two-phase pulse input in event counter mode
electrical characteristics 7751 group users manual 15C9 timer b input (count input in event counter mode) 15.5 internal peripheral devices timer b input (pulse period measurement mode) limits min. 80 40 40 160 80 80 max. ns ns ns ns ns ns unit parameter symbol tbi in input cycle time (one edge count) tbi in input high-level pulse width (one edge count) tbi in input low-level pulse width (one edge count) tbi in input cycle time (both edges count) tbi in input high-level pulse width (both edges count) tbi in input low-level pulse width (both edges count) limits t c(tb) t w(tbh) t w(tbl) tbi in input cycle time tbi in input high-level pulse width tbi in input low-level pulse width min. max. unit symbol parameter data formula (min.) f(x in ) 40 mhz f(x in ) 25 mhz when f divided by 2 selected as clock source for peripheral devices f(x in ) 25 mhz when f selected as clock source for peripheral devices 400 640 320 ns 16 5 10 9 f(x in ) 16 5 10 9 f(x in ) 8 5 10 9 f(x in ) f(x in ) 40 mhz f(x in ) 25 mhz when f divided by 2 selected as clock source for peripheral devices f(x in ) 25 mhz when f selected as clock source for peripheral devices 200 320 160 ns 8 5 10 9 f(x in ) 8 5 10 9 f(x in ) 4 5 10 9 f(x in ) f(x in ) 40 mhz f(x in ) 25 mhz when f divided by 2 selected as clock source for peripheral devices f(x in ) 25 mhz when f selected as clock source for peripheral devices 200 320 160 ns 8 5 10 9 f(x in ) 8 5 10 9 f(x in ) 4 5 10 9 f(x in ) notes 1: tbi in input cycle time must be 4 cycles or more of count source, tbi in input high-level pulse width must be 2 cycles or more of count source, tbi in input low-level pulse width must be 2 cycles or more of count source. 2: the limits in the upper row of the table are the values when f(x in ) is 40 mhz and the count source is f 4 . the limits in the middle row of the table are the values when f(x in ) is 25 mhz and the count source is f 4 . the limits in the lower row of the table are the values when f(x in ) is 25 mhz and the count source is f 2 . t c(tb) t w(tbh) t w(tbl) t c(tb) t w(tbh) t w(tbl)
electrical characteristics 7751 group users manual 15C10 timer b input (pulse width measurement mode) limits t c(tb) t w(tbh) t w(tbl) tbi in input cycle time tbi in input high-level pulse width tbi in input low-level pulse width min. max. unit symbol parameter data formula (min.) f(x in ) 40 mhz f(x in ) 25 mhz when f divided by 2 selected as clock source for peripheral devices f(x in ) 25 mhz when f selected as clock source for peripheral devices 400 640 320 ns 16 5 10 9 f(x in ) 16 5 10 9 f(x in ) 8 5 10 9 f(x in ) f(x in ) 40 mhz f(x in ) 25 mhz when f divided by 2 selected as clock source for peripheral devices f(x in ) 25 mhz when f selected as clock source for peripheral devices 200 320 160 ns 8 5 10 9 f(x in ) 8 5 10 9 f(x in ) 4 5 10 9 f(x in ) f(x in ) 40 mhz f(x in ) 25 mhz when f divided by 2 selected as clock source for peripheral devices f(x in ) 25 mhz when f selected as clock source for peripheral devices 200 320 160 ns 8 5 10 9 f(x in ) 8 5 10 9 f(x in ) 4 5 10 9 f(x in ) notes 1: tbi in input cycle time must be 4 cycles or more of count source, tbi in input high-level pulse width must be 2 cycles or more of count source, tbi in input low-level pulse width must be 2 cycles or more of count source. 2: the limits in the upper row of the table are the values when f(x in ) is 40 mhz and the count source is f 4 . the limits in the middle row of the table are the values when f(x in ) is 25 mhz and the count source is f 4 . the limits in the lower row of the table are the values when f(x in ) is 25 mhz and the count source is f 2 . 15.5 internal peripheral devices a-d trigger input limits min. 1000 125 max. ns ns unit symbol parameter _____ ad trg input cycle time (minimum allowable trigger) _____ ad trg input low-level pulse width t c(ad) t w(adl)
electrical characteristics 7751 group users manual 15C11 15.5 internal peripheral devices ____ external interrupt int i input serial i/o limits ns ns ns ns ns ns ns clk i input cycle time clk i input high-level pulse width clk i input low-level pulse width txd i output delay time txd i hold time rxd i input setup time rxd i input hold time t c(ck) t w(ckh) t w(ckl) t d(cCq) t h(cCq) t su(dCc) t h(cCd) symbol parameter unit max. 80 min. 200 100 100 0 20 90 limits min. 250 250 max. ns ns unit parameter symbol ___ int i input high-level pulse width ___ int i input low-level pulse width t w(inh) t w(inl)
electrical characteristics 7751 group users manual 15C12 15.5 internal peripheral devices test conditions ?v cc = 5 v10% ?input timing voltage : v il = 1.0 v, v ih = 4.0 v ?output timing voltage : v ol = 0.8 v, v oh = 2.0 v tbi in input t c(tb) t w(tbh) t w(tbl) t c(ad) t w(adl) ad trg input t w(inl) t w(inh) int i input t c(ck) t w(ckh) t w(ckl) t h(cCq) t su(dCc) clk i input txd i output rxd i input t d(cCq) t h(cCd) internal peripheral devices
electrical characteristics 7751 group users manual 15C13 15.6 ready and hold timing requirements (v cc = 5 v 10%, v ss = 0 v, ta = C20 to 85 c, f(x in ) = 40 mhz, unless otherwise noted) 15.6 ready and hold switching characteristics (v cc = 5 v 10%, v ss = 0 v, ta = C20 to 85 c, f(x in ) = 40 mhz, unless otherwise noted) limits min. 40 40 0 0 max. ns ns ns ns unit parameter ____ rdy input setup time _____ hold input setup time ____ rdy input hold time _____ hold input hold time limits unit parameter _____ hlda output delay time min. max. 50 ns note: for test conditions, refer to figure 15.15.1. t d( f 1 Chlda) t su(rdyC f 1 ) t su(holdC f 1 ) t h( f 1 Crdy) t h( f 1 Chold) symbol symbol
electrical characteristics 7751 group users manual 15C14 15.6 ready and hold ?v cc = 5 v10% ?input timing voltage : v il = 1.0 v, v ih = 4.0 v ?output timing voltage : v ol = 0.8 v, v oh = 2.0 v 1 when 2- access in low-speed running 1 when 3- access and 4- access in low-speed running, and 4 - access in high-speed running rdy input l ready function e output e output rdy input 1 when 2- access in high-speed running e output rdy input t su(rdyC 1 ) t h( 1 Crdy) t su(rdyC 1 ) t h( 1 Crdy) t su(rdyC 1 ) t h( 1 Crdy) test conditions
electrical characteristics 7751 group users manual 15C15 15.6 ready and hold l ready function ?v cc = 5 v10% ?input timing voltage : v il = 1.0 v, v ih = 4.0 v ?output timing voltage : v ol = 0.8 v, v oh = 2.0 v when 3- access in high-speed running rdy input e output 1 t su(rdyC 1 ) t h( 1 Crdy) 1 when 5- access in high-speed running e output rdy input t su(rdyC 1 ) t h( 1 Crdy) 1 hold input hlda output t h( 1 Chold) t d( 1 Chlda) 1 ) l hold function t d( 1 Chlda) t su(holdC test conditions
electrical characteristics 7751 group users manual 15C16 15.7 single-chip mode ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns 8 8 25 t c /2C8 t c /2C8 60 60 60 60 60 60 60 60 60 0 0 0 0 0 0 0 0 0 min. max. external clock input cycle time external clock input high-level pulse width external clock input low-level pulse width external clock rise time external clock fall time port p0 input setup time port p1 input setup time port p2 input setup time port p3 input setup time port p4 input setup time port p5 input setup time port p6 input setup time port p7 input setup time port p8 input setup time port p0 input hold time port p1 input hold time port p2 input hold time port p3 input hold time port p4 input hold time port p5 input hold time port p6 input hold time port p7 input hold time port p8 input hold time symbol parameter unit limits max. min. 60 60 60 60 60 60 60 60 60 ns ns ns ns ns ns ns ns ns limits unit parameter symbol note: for test conditions, refer to figure 15.15.1. port p0 data output delay time port p1 data output delay time port p2 data output delay time port p3 data output delay time port p4 data output delay time port p5 data output delay time port p6 data output delay time port p7 data output delay time port p8 data output delay time switching characteristics (v cc = 5 v 10%, v ss = 0 v, ta = C20 to 85 c, unless otherwise noted) 15.7 single-chip mode timing requirements (v cc = 5 v 10%, v ss = 0 v, ta = C20 to 85 c, unless otherwise noted) t d(eCp0q) t d(eCp1q) t d(eCp2q) t d(eCp3q) t d(eCp4q) t d(eCp5q) t d(eCp6q) t d(eCp7q) t d(eCp8q) t c t w(h) t w(l) t r t f t su(p0dCe) t su(p1dCe) t su(p2dCe) t su(p3dCe) t su(p4dCe) t su(p5dCe) t su(p6dCe) t su(p7dCe) t su(p8dCe) t h(eCp0d) t h(eCp1d) t h(eCp2d) t h(eCp3d) t h(eCp4d) t h(eCp5d) t h(eCp6d) t h(eCp7d) t h(eCp8d)
electrical characteristics 7751 group users manual 15C17 15.7 single-chip mode t d(eCp0q) t su(p0dCe) t h(eCp0d) t d(eCp1q) t su(p1dCe) t h(eCp1d) t d(eCp2q) t su(p2dCe) t h(eCp2d) t d(eCp3q) t su(p3dCe) t h(eCp3d) t w(h) t c t r t f e port p0 output x in t d(eCp4q) t su(p4dCe) t h(eCp4d) t d(eCp5q) t su(p5dCe) t h(eCp5d) t d(eCp6q) t su(p6dCe) t h(eCp6d) t d(eCp7q) t su(p7dCe) t h(eCp7d) t d(eCp8q) t su(p8dCe) t h(eCp8d) t w(l) single-chip mode test conditions ?v cc = 5 v 10% ?input timing voltage ?output timing voltage : v il = 1.0 v, v ih = 4.0 v : v ol = 0.8 v, v oh = 2.0 v port p0 input port p1 output port p1 input port p2 output port p2 input port p3 output port p3 input port p4 output port p4 input port p5 output port p5 input port p6 output port p6 input port p7 output port p7 input port p8 output port p8 input
electrical characteristics 7751 group users manual 15C18 ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns 15.8 memory expansion mode and microprocessor mode : when 2- f access in low-speed running 15.8 memory expansion mode and microprocessor mode : when 2- f access in low-speed running timing requirements (v cc = 5 v 10%, v ss = 0 v, ta = C20 to 85 c, f(x in ) = 25 mhz, unless otherwise noted) limits min. max. unit symbol parameter data formula (max.) 8 8 40 t c /2C8 t c /2C8 30 30 60 60 60 60 60 0 0 0 0 0 0 0 55 3 5 10 9 f(x in ) C65 external clock input cycle time external clock input high-level pulse width external clock input low-level pulse width external clock rise time external clock fall time port p1 input setup time port p2 input setup time port p4 input setup time port p5 input setup time port p6 input setup time port p7 input setup time port p8 input setup time port p1 input hold time port p2 input hold time port p4 input hold time port p5 input hold time port p6 input hold time port p7 input hold time port p8 input hold time port pi data setup time with address stabilized t c t w(h) t w(l) t r t f t su(p1dCe) t su(p2dCe) t su(p4dCe) t su(p5dCe) t su(p6dCe) t su(p7dCe) t su(p8dCe) t h(eCp1d) t h(eCp2d) t h(eCp4d) t h(eCp5d) t h(eCp6d) t h(eCp7d) t h(eCp8d) t su(p0a/p1a/p2aCp1d/p2d)
electrical characteristics 7751 group users manual 15C19 switching characteristics (v cc = 5 v 10%, v ss = 0 v, ta = C20 to 85 c, f(x in ) = 25 mhz, unless otherwise noted) ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns limits min. max. unit symbol parameter data formula (min.) port p4 data output delay time port p5 data output delay time port p6 data output delay time port p7 data output delay time port p8 data output delay time f high-level pulse width f low-level pulse width f 1 output delay time _ e low-level pulse width port p0 address output delay time port p1 data output delay time (byte = l) port p1 floating start delay time (byte = l) port p1 address output delay time port p1 address output delay time port p2 data output delay time port p2 floating start delay time port p2 address output delay time port p2 address output delay time ale output delay time ale output delay time ale pulse width ____ bhe output delay time __ r/w output delay time 60 60 60 60 60 18 35 5 35 5 20 20 0 55 12 12 5 12 5 20 4 22 20 20 C 20 C 20 C 18 1 5 10 9 f(x in ) 1 5 10 9 f(x in ) 1 5 10 9 f(x in ) C 20 1 5 10 9 f(x in ) C 35 1 5 10 9 f(x in ) C 28 1 5 10 9 f(x in ) C 35 1 5 10 9 f(x in ) C 28 1 5 10 9 f(x in ) C 28 1 5 10 9 f(x in ) C 25 2 5 10 9 f(x in ) C 20 1 5 10 9 f(x in ) C 20 1 5 10 9 f(x in ) 15.8 memory expansion mode and microprocessor mode : when 2- f access in low-speed running note: for test conditions, refer to figure 15.15.1. t d(eCp4q) t d(eCp5q) t d(eCp6q) t d(eCp7q) t d(eCp8q) t w( f h) t w( f l) t d(eC f 1 ) t w(el) t d(p0aCe) t d(eCp1q) t pxz(eCp1z) t d(p1aCe) t d(p1aCale) t d(eCp2q) t pxz(eCp2z) t d(p2aCe) t d(p2aCale) t d(eCale) t d(aleCe) t w(ale) t d(bheCe) t d(r/wCe)
electrical characteristics 7751 group users manual 15C20 15.8 memory expansion mode and microprocessor mode : when 2- f access in low-speed running switching characteristics (v cc = 5 v 10%, v ss = 0 v, ta = C20 to 85 c, f(x in ) = 25 mhz, unless otherwise noted) ns ns ns ns ns ns ns ns ns ns limits min. max. unit symbol parameter data formula (min.) 18 9 18 18 18 9 18 18 18 18 port p0 address hold time port p1 address hold time (byte = l) port p1 data hold time (byte = l) port p1 floating release delay time (byte = l) port p1 address hold time (byte = h) port p2 address hold time port p2 data hold time port p2 floating release delay time ____ bhe hold time __ r/w hold time C 22 1 5 10 9 f(x in ) C 22 1 5 10 9 f(x in ) C 22 1 5 10 9 f(x in ) C 22 1 5 10 9 f(x in ) C 22 1 5 10 9 f(x in ) C 22 1 5 10 9 f(x in ) C 22 1 5 10 9 f(x in ) C 22 1 5 10 9 f(x in ) note: for test conditions, refer to figure 15.15.1. t h(eCp0a) t h(aleCp1a) t h(eCp1q) t pzx(eCp1z) t h(eCp1a) t h(aleCp2a) t h(eCp2q) t pzx(eCp2z) t h(eCbhe) t h(eCrw)
electrical characteristics 7751 group users manual 15C21 15.8 memory expansion mode and microprocessor mode : when 2- f access in low-speed running t w( t d(p1aCe) t d(p1aCe) t w(l) t w(h) t r t f t c t w( t w(el) t d(eC 1 ) t d(eC 1 ) t h(eCp0a) t h(eCp1a) t d(p0aCe) t h(eCp1q) t d(eCp1q) address address data t h(eCp 2q ) t d(eCp 2q ) t d(p2aCe) data address address t h(aleCp1a) t d(p1aCale) t h(aleCp2a) t d(p2aCale) t h(eCbh e) t d(b h e Ce) t d(aleCe) t d(eCa le ) t w(ale) t d(r / wCe) t h(eCr / w t d(eCpi q) memory expansion mode and microprocessor mode : when 2- access in low-speed running x in 1 address output a 0 Ca 7 bhe output port pi output (i = 4C8) test conditions (p4Cp8) ?v cc = 5 v10% ? input timing voltage : v il = 1.0 v, v ih = 4.0 v ? output timing voltage : v ol = 0.8 v, v oh = 2.0 v e address output a 8 Ca 15 (byte = h) data input d 8 Cd 15 (byte = l) address/data output a 16 /d 0 Ca 23 /d 7 ale output r/w output data input d 0 Cd 7 address/data output a 8 /d 8 Ca 15 /d 15 (byte = l) test conditions ( 1 , e, p0Cp3) ?v cc = 5 v10% ?output timing voltage : v ol = 0.8 v, v oh = 2.0 v ?data input : v il = 0.8 v, v ih = 2.5 v h) l) )
electrical characteristics 7751 group users manual 15C22 15.8 memory expansion mode and microprocessor mode : when 2- f access in low-speed running t w( t su(p1dCe) t d(p0aCe) data t d(p1aCe) t d(p1aCe) t w(l) t w(h) t r t f t c t w( t w(el) t d(eC 1 ) t d(eC 1 ) t h(eCp0a) t h(eCp1a) t pzx(eCp1z) t pxz(eCp1z) address address address t d(p1aCale) t h(eCbhe) t d(bheCe) t d(aleCe) t d(eCale) t w(ale) t d(r/wCe) t h(eCr/w) memory expansion mode and microprocessor mode : when 2- access in low-speed running t h(eCp1d) t h(aleCp1a) data t d(p2aCe) t pzx(eCp2z) t h(eCp2d) address t h(eCpid) t su(pidCe) x in 1 address output a 0 Ca 7 bhe output test conditions ( 1 , e, p0Cp3) ?v cc = 5 v10% ?output timing voltage : v ol = 0.8 v, v oh = 2.0 v ?data input : v il = 0.8 v, v ih = 2.5 v port pi output (i = 4C8) test conditions (p4Cp8) ?v cc = 5 v10% ?input timing voltage : v il = 1.0 v, v ih = 4.0 v ?output timing voltage : v ol = 0.8 v, v oh = 2.0 v e address output a 8 Ca 15 (byte = h) data input d 8 Cd 15 (byte = l) address/data output a 16 /d 0 Ca 23 /d 7 ale output r/w output data input d 0 Cd 7 address/data output a 8 /d 8 Ca 15 /d 15 (byte = l) t su(p2dCe) t pxz(eCp2z) t h(aleCp2a) t su(p0a/p1a/p2aCp1d/p2d) t d(p2aCale) l) h)
electrical characteristics 7751 group users manual 15C23 15.9 memory expansion mode and microprocessor mode : when 3- f access in low-speed running 15.9 memory expansion mode and microprocessor mode : when 3- f access in low-speed running timing requirements (v cc = 5 v 10%, v ss = 0 v, ta = C20 to 85 c, f(x in ) = 25 mhz, unless otherwise noted) ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns limits min. max. unit symbol parameter data formula (max.) 8 8 40 t c /2C8 t c /2C8 30 30 60 60 60 60 60 0 0 0 0 0 0 0 135 5 5 10 9 f(x in ) C65 external clock input cycle time external clock input high-level pulse width external clock input low-level pulse width external clock rise time external clock fall time port p1 input setup time port p2 input setup time port p4 input setup time port p5 input setup time port p6 input setup time port p7 input setup time port p8 input setup time port p1 input hold time port p2 input hold time port p4 input hold time port p5 input hold time port p6 input hold time port p7 input hold time port p8 input hold time port pi data setup time with address stabilized t c t w(h) t w(l) t r t f t su(p1dCe) t su(p2dCe) t su(p4dCe) t su(p5dCe) t su(p6dCe) t su(p7dCe) t su(p8dCe) t h(eCp1d) t h(eCp2d) t h(eCp4d) t h(eCp5d) t h(eCp6d) t h(eCp7d) t h(eCp8d) t su(p0a/p1a/p2aCp1d/p2d)
electrical characteristics 7751 group users manual 15C24 switching characteristics (v cc = 5 v 10%, v ss = 0 v, ta = C20 to 85 c, f(x in ) = 25 mhz, unless otherwise noted) ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns limits min. max. unit symbol parameter data formula (min.) port p4 data output delay time port p5 data output delay time port p6 data output delay time port p7 data output delay time port p8 data output delay time f high-level pulse width f low-level pulse width f 1 output delay time _ e low-level pulse width port p0 address output delay time port p1 data output delay time (byte = l) port p1 floating start delay time (byte = l) port p1 address output delay time port p1 address output delay time port p2 data output delay time port p2 floating start delay time port p2 address output delay time port p2 address output delay time ale output delay time ale output delay time ale pulse width ____ bhe output delay time __ r/w output delay time 60 60 60 60 60 18 35 5 35 5 20 20 0 135 12 12 5 12 5 20 4 22 20 20 C 20 C 20 C 18 1 5 10 9 f(x in ) 1 5 10 9 f(x in ) 1 5 10 9 f(x in ) C 20 1 5 10 9 f(x in ) C 35 1 5 10 9 f(x in ) C 28 1 5 10 9 f(x in ) C 35 1 5 10 9 f(x in ) C 28 1 5 10 9 f(x in ) C 28 1 5 10 9 f(x in ) C 25 4 5 10 9 f(x in ) C 20 1 5 10 9 f(x in ) C 20 1 5 10 9 f(x in ) note: for test conditions, refer to figure 15.15.1. 15.9 memory expansion mode and microprocessor mode : when 3- f access in low-speed running t d(eCp4q) t d(eCp5q) t d(eCp6q) t d(eCp7q) t d(eCp8q) t w( f h) t w( f l) t d(eC f 1 ) t w(el) t d(p0aCe) t d(eCp1q) t pxz(eCp1z) t d(p1aCe) t d(p1aCale) t d(eCp2q) t pxz(eCp2z) t d(p2aCe) t d(p2aCale) t d(eCale) t d(aleCe) t w(ale) t d(bheCe) t d(r/wCe)
electrical characteristics 7751 group users manual 15C25 15.9 memory expansion mode and microprocessor mode : when 3- f access in low-speed running switching characteristics (v cc = 5 v 10%, v ss = 0 v, ta = C20 to 85 c, f(x in ) = 25 mhz, unless otherwise noted) ns ns ns ns ns ns ns ns ns ns limits min. max. unit symbol parameter data formula (min.) 18 9 18 18 18 9 18 18 18 18 port p0 address hold time port p1 address hold time (byte = l) port p1 data hold time (byte = l) port p1 floating release delay time (byte = l) port p1 address hold time (byte = h) port p2 address hold time port p2 data hold time port p2 floating release delay time ____ bhe hold time __ r/w hold time C 22 1 5 10 9 f(x in ) C 22 1 5 10 9 f(x in ) C 22 1 5 10 9 f(x in ) C 22 1 5 10 9 f(x in ) C 22 1 5 10 9 f(x in ) C 22 1 5 10 9 f(x in ) C 22 1 5 10 9 f(x in ) C 22 1 5 10 9 f(x in ) note: for test conditions, refer to figure 15.15.1. t h(eCp0a) t h(aleCp1a) t h(eCp1q) t pzx(eCp1z) t h(eCp1a) t h(aleCp2a) t h(eCp2q) t pzx(eCp2z) t h(eCbhe) t h(eCrw)
electrical characteristics 7751 group users manual 15C26 15.9 memory expansion mode and microprocessor mode : when 3- f access in low-speed running t w( t d(p1aCe) t d(p1aCe) t w(l) t w(h) t r t f t c t w( t w(el) t d(eC 1 ) t d(eC 1 ) t h(eCp0a) t h(eCp1a) t d(p0aCe) t h(eCp1q) t d(eCp1q) address address data t h(eCp2q) t d(eCp2q) t d(p2aCe) data address t h(aleCp1a) t d(p1aCale) t h(aleCp2a) t d(p2aCale) t h(eCbhe) t d(bheCe) t d(aleCe) t d(eCale) t w(ale) t d(r/wCe) t h(eCr/w) t d(eCpiq) memory expansion mode and microprocessor mode : when 3- access in low-speed running address x in 1 address output a 0 Ca 7 bhe output port pi output (i = 4C8) test conditions (p4Cp8) ?v cc = 5 v10% ?input timing voltage : v il = 1.0 v, v ih = 4.0 v ?output timing voltage : v ol = 0.8 v, v oh = 2.0 v e address output a 8 Ca 15 (byte = h) data input d 8 Cd 15 (byte = l) address/data output a 16 /d 0 Ca 23 /d 7 ale output r/w output data input d 0 Cd 7 address/data output a 8 /d 8 Ca 15 /d 15 (byte = l) test conditions ( 1 , e, p0Cp3) ?v cc = 5 v10% ?output timing voltage : v ol = 0.8 v, v oh = 2.0 v ?data input : v il = 0.8 v, v ih = 2.5 v l) h)
electrical characteristics 7751 group users manual 15C27 15.9 memory expansion mode and microprocessor mode : when 3- f access in low-speed running t w( t su(p1dCe) t d(p0aCe) data t d(p1aCe) t d(p1aCe) t w(l) t w(h) t r t f t c t w( t w(el) t d(eC 1 ) t d(eC 1 ) t h(eCp0a) t h(eCp1a) t pzx(eCp1z) t pxz(eCp1z) address address address t d(p1aCale) t h(eCbhe) t d(bheCe) t d(aleCe) t d(eCale) t w(ale) t d(r/wCe) t h(eCr/w) memory expansion mode and microprocessor mode : when 3- access in low-speed running t h(eCp1d) t h(aleCp1a) data t d(p2aCe) t pzx(eCp2z) t pxz(eCp2z) t h(eCp2d) t h(aleCp2a) address t h(eCpid) t su(pidCe) x in 1 address output a 0 Ca 7 bhe output port pi output (i = 4C8) test conditions (p4Cp8) ?v cc = 5 v10% ? input timing voltage : v il = 1.0 v, v ih = 4.0 v ?output timing voltage : v ol = 0.8 v, v oh = 2.0 v e address output a 8 Ca 15 (byte = h) data input d 8 Cd 15 (byte = l) address/data output a 16 /d 0 Ca 23 /d 7 ale output r/w output data input d 0 Cd 7 address/data output a 8 /d 8 Ca 15 /d 15 (byte = l) test conditions ( 1 , e, p0Cp3) ?v cc = 5 v10% ?output timing voltage : v ol = 0.8 v, v oh = 2.0 v ?data input : v il = 0.8 v, v ih = 2.5 v t su(p2dCe) t d(p2aCale) t su(p0a/p1a/p2aCp1d/p2d) l) h)
electrical characteristics 7751 group users manual 15C28 15.10 memory expansion mode and microprocessor mode : when 4- f access in low-speed running 15.10 memory expansion mode and microprocessor mode : when 4- f access in low-speed running timing requirements (v cc = 5 v 10%, v ss = 0 v, ta = C20 to 85 c, f(x in ) = 25 mhz, unless otherwise noted) ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns limits min. max. unit symbol parameter data formula (max.) 8 8 40 t c /2C8 t c /2C8 30 30 60 60 60 60 60 0 0 0 0 0 0 0 215 7 5 10 9 f(x in ) C65 external clock input cycle time external clock input high-level pulse width external clock input low-level pulse width external clock rise time external clock fall time port p1 input setup time port p2 input setup time port p4 input setup time port p5 input setup time port p6 input setup time port p7 input setup time port p8 input setup time port p1 input hold time port p2 input hold time port p4 input hold time port p5 input hold time port p6 input hold time port p7 input hold time port p8 input hold time port pi data setup time with address stabilized t c t w(h) t w(l) t r t f t su(p1dCe) t su(p2dCe) t su(p4dCe) t su(p5dCe) t su(p6dCe) t su(p7dCe) t su(p8dCe) t h(eCp1d) t h(eCp2d) t h(eCp4d) t h(eCp5d) t h(eCp6d) t h(eCp7d) t h(eCp8d) t su(p0a/p1a/p2aCp1d/p2d)
electrical characteristics 7751 group users manual 15C29 15.10 memory expansion mode and microprocessor mode : when 4- f access in low-speed running switching characteristics (v cc = 5 v 10%, v ss = 0 v, ta = C20 to 85 c, f(x in ) = 25 mhz, unless otherwise noted) ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns limits min. max. unit symbol parameter data formula (min.) port p4 data output delay time port p5 data output delay time port p6 data output delay time port p7 data output delay time port p8 data output delay time f high-level pulse width f low-level pulse width f 1 output delay time _ e low-level pulse width port p0 address output delay time port p1 data output delay time (byte = l) port p1 floating start delay time (byte = l) port p1 address output delay time port p1 address output delay time port p2 data output delay time port p2 floating start delay time port p2 address output delay time port p2 address output delay time ale output delay time ale output delay time ale pulse width ____ bhe output delay time __ r/w output delay time 60 60 60 60 60 18 35 5 35 5 20 20 0 135 92 92 52 92 52 20 4 62 100 100 C 20 C 20 C 18 3 5 10 9 f(x in ) 3 5 10 9 f(x in ) 2 5 10 9 f(x in ) C 20 1 5 10 9 f(x in ) C 28 2 5 10 9 f(x in ) C 28 3 5 10 9 f(x in ) 2 5 10 9 f(x in ) C 28 3 5 10 9 f(x in ) C 28 3 5 10 9 f(x in ) C 25 4 5 10 9 f(x in ) C 20 1 5 10 9 f(x in ) C 20 1 5 10 9 f(x in ) note: for test conditions, refer to figure 15.15.1. C 28 t d(eCp4q) t d(eCp5q) t d(eCp6q) t d(eCp7q) t d(eCp8q) t w( f h) t w( f l) t d(eC f 1 ) t w(el) t d(p0aCe) t d(eCp1q) t pxz(eCp1z) t d(p1aCe) t d(p1aCale) t d(eCp2q) t pxz(eCp2z) t d(p2aCe) t d(p2aCale) t d(eCale) t d(aleCe) t w(ale) t d(bheCe) t d(r/wCe)
electrical characteristics 7751 group users manual 15C30 15.10 memory expansion mode and microprocessor mode : when 4- f access in low-speed running switching characteristics (v cc = 5 v 10%, v ss = 0 v, ta = C20 to 85 c, f(x in ) = 25 mhz, unless otherwise noted) ns ns ns ns ns ns ns ns ns ns limits min. max. unit symbol parameter data formula (min.) 18 25 18 18 18 25 18 18 18 18 port p0 address hold time port p1 address hold time (byte = l) port p1 data hold time (byte = l) port p1 floating release delay time (byte = l) port p1 address hold time (byte = h) port p2 address hold time port p2 data hold time port p2 floating release delay time ____ bhe hold time __ r/w hold time C 22 1 5 10 9 f(x in ) C 22 1 5 10 9 f(x in ) C 22 1 5 10 9 f(x in ) C 22 1 5 10 9 f(x in ) C 22 1 5 10 9 f(x in ) C 22 1 5 10 9 f(x in ) C 22 1 5 10 9 f(x in ) C 22 1 5 10 9 f(x in ) note: for test conditions, refer to figure 15.15.1. C 15 1 5 10 9 f(x in ) C 15 1 5 10 9 f(x in ) t h(eCp0a) t h(aleCp1a) t h(eCp1q) t pzx(eCp1z) t h(eCp1a) t h(aleCp2a) t h(eCp2q) t pzx(eCp2z) t h(eCbhe) t h(eCrw)
electrical characteristics 7751 group users manual 15C31 15.10 memory expansion mode and microprocessor mode : when 4- f access in low-speed running e t w( t d(p1aCe) t d(p1aCe) t d(p0aCe) t w(l) t w(h) t r t f t c t w( t w(el) t d(eC 1 ) t d(eC 1 ) t h(eCp0a) t h(eCp1a) t h(eCp1q) t d(eCp 1q ) address address data t h(eCp2q) t d(eCp2q) t d(p2aCe) data t h(aleCp1a) t d(p1aCale) t h(aleCp2a) t d(p2aCale) t h(eCbhe) t d(bheCe) t w(ale) t d(aleCe) t d(eCale) t d(r/wCe) t h(eCr/w) t d(eCpiq) memory expansion mode and microprocessor mode : when 4- access in low-speed running address address x in 1 address output a 0 Ca 7 bhe output port pi output (i = 4C8) test conditions (p4Cp8) ?v cc = 5 v10% ? input timing voltage : v il = 1.0 v, v ih = 4.0 v ? output timing voltage : v ol = 0.8 v, v oh = 2.0 v e address output a 8 Ca 15 (byte = h) data input d 8 Cd 15 (byte = l) address/data output a 16 /d 0 Ca 23 /d 7 ale output r/w output data input d 0 Cd 7 address/data output a 8 /d 8 Ca 15 /d 15 (byte = l) test conditions ( 1 , e, p0Cp3) ?v cc = 5 v10% ?output timing voltage : v ol = 0.8 v, v oh = 2.0 v ?data input : v il = 0.8 v, v ih = 2.5 v l) h)
electrical characteristics 7751 group users manual 15C32 15.10 memory expansion mode and microprocessor mode : when 4- f access in low-speed running e t w( t d(p1aCe) t d(p1aCe) t w(l) t w(h) t r t f t c t w( t w(el) t d(eC 1 ) t d(eC 1 ) t h(eCp0a) t h(eCp1a) t d(p0aCe) t pzx(eCp1z) t pxz(eCp1z) address address address t h(aleCp1a) t d(p1aCale) t h(eCbhe) t d(bheCe) t d(aleCe) t d(eCale) t w(ale) t d(r/wCe) t h(eCr/w) t su(pidCe) memory expansion mode and microprocessor mode : when 4- access in low-speed running data t su(p1dCe) t h(eCp1d) t d(p2aCe) t pzx(eCp2z) t pxz(eCp2z) address t h(aleCp2a) data t h(eCp2d) t h(eCpid) x in 1 address output a 0 Ca 7 bhe output port pi output (i = 4C8) test conditions (p4Cp8) ?v cc = 5 v10% ?input timing voltage : v il = 1.0 v, v ih = 4.0 v ?output timing voltage : v ol = 0.8 v, v oh = 2.0 v e address output a 8 Ca 15 (byte = h) data input d 8 Cd 15 (byte = l) address/data output a 16 /d 0 Ca 23 /d 7 ale output r/w output data input d 0 Cd 7 address/data output a 8 /d 8 Ca 15 /d 15 (byte = l) test conditions ( 1 , e, p0Cp3) ?v cc = 5 v10% ?output timing voltage : v ol = 0.8 v, v oh = 2.0 v ?data input : v il = 0.8 v, v ih = 2.5 v t su(p2dCe) t d(p2aCale) t su(p0a/p1a/p2aCp1d/p2d) l) h)
electrical characteristics 7751 group users manual 15C33 ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns 15.11 memory expansion mode and microprocessor mode : when 3- f access in high-speed running 15.11 memory expansion mode and microprocessor mode : when 3- f access in high-speed running timing requirements (v cc = 5 v 10%, v ss = 0 v, ta = C20 to 85 c, f(x in ) = 40 mhz, unless otherwise noted) limits min. max. unit symbol parameter data formula (max.) 8 8 25 t c /2C8 t c /2C8 30 30 60 60 60 60 60 0 0 0 0 0 0 0 50 5 5 10 9 f(x in ) C75 external clock input cycle time external clock input high-level pulse width external clock input low-level pulse width external clock rise time external clock fall time port p1 input setup time port p2 input setup time port p4 input setup time port p5 input setup time port p6 input setup time port p7 input setup time port p8 input setup time port p1 input hold time port p2 input hold time port p4 input hold time port p5 input hold time port p6 input hold time port p7 input hold time port p8 input hold time port pi data setup time with address stabilized t c t w(h) t w(l) t r t f t su(p1dCe) t su(p2dCe) t su(p4dCe) t su(p5dCe) t su(p6dCe) t su(p7dCe) t su(p8dCe) t h(eCp1d) t h(eCp2d) t h(eCp4d) t h(eCp5d) t h(eCp6d) t h(eCp7d) t h(eCp8d) t su(p0a/p1a/p2aCp1d/p2d)
electrical characteristics 7751 group users manual 15C34 1 5 10 9 2 5 f(x in ) switching characteristics (v cc = 5 v 10%, v ss = 0 v, ta = C20 to 85 c, f(x in ) = 40 mhz, unless otherwise noted) ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns limits min. max. unit symbol parameter data formula (min.) port p4 data output delay time port p5 data output delay time port p6 data output delay time port p7 data output delay time port p8 data output delay time f high-level pulse width f low-level pulse width f 1 output delay time _ e low-level pulse width port p0 address output delay time port p1 data output delay time (byte = l) port p1 floating start delay time (byte = l) port p1 address output delay time port p1 address output delay time port p2 data output delay time port p2 floating start delay time port p2 address output delay time port p2 address output delay time ale output delay time ale output delay time ale pulse width ____ bhe output delay time __ r/w output delay time 60 60 60 60 60 18 35 5 35 5 5 5 0 50 15 15 5 15 5 10 5 10 20 20 C 30 C 30 C 15 2 5 10 9 f(x in ) 2 5 10 9 f(x in ) 1 5 10 9 f(x in ) C 15 1 5 10 9 f(x in ) C 20 1 5 10 9 f(x in ) C 35 2 5 10 9 f(x in ) C 20 1 5 10 9 f(x in ) C 35 2 5 10 9 f(x in ) 2 5 10 9 f(x in ) C 25 3 5 10 9 f(x in ) C 20 1 5 10 9 f(x in ) C 20 1 5 10 9 f(x in ) 15.11 memory expansion mode and microprocessor mode : when 3- f access in high-speed running note: for test conditions, refer to figure 15.15.1. C 35 C 7.5 t d(eCp4q) t d(eCp5q) t d(eCp6q) t d(eCp7q) t d(eCp8q) t w( f h) t w( f l) t d(eC f 1 ) t w(el) t d(p0aCe) t d(eCp1q) t pxz(eCp1z) t d(p1aCe) t d(p1aCale) t d(eCp2q) t pxz(eCp2z) t d(p2aCe) t d(p2aCale) t d(eCale) t d(aleCe) t w(ale) t d(bheCe) t d(r/wCe)
electrical characteristics 7751 group users manual 15C35 15.11 memory expansion mode and microprocessor mode : when 3- f access in high-speed running switching characteristics (v cc = 5 v 10%, v ss = 0 v, ta = C20 to 85 c, f(x in ) = 40 mhz, unless otherwise noted) ns ns ns ns ns ns ns ns ns ns limits min. max. unit symbol parameter data formula (min.) 15 10 15 15 15 10 15 15 15 15 port p0 address hold time port p1 address hold time (byte = l) port p1 data hold time (byte = l) port p1 floating release delay time (byte = l) port p1 address hold time (byte = h) port p2 address hold time port p2 data hold time port p2 floating release delay time ____ bhe hold time __ r/w hold time C 10 1 5 10 9 f(x in ) C 10 1 5 10 9 f(x in ) C 10 1 5 10 9 f(x in ) C 10 1 5 10 9 f(x in ) C 10 1 5 10 9 f(x in ) C 10 1 5 10 9 f(x in ) C 10 1 5 10 9 f(x in ) C 10 1 5 10 9 f(x in ) note: for test conditions, refer to figure 15.15.1. C 15 1 5 10 9 f(x in ) C 15 1 5 10 9 f(x in ) t h(eCp0a) t h(aleCp1a) t h(eCp1q) t pzx(eCp1z) t h(eCp1a) t h(aleCp2a) t h(eCp2q) t pzx(eCp2z) t h(eCbhe) t h(eCrw)
electrical characteristics 7751 group users manual 15C36 15.11 memory expansion mode and microprocessor mode : when 3- f access in high-speed running t w( address address t w(l) t w(h) t r t f t c t w( t w(el) t d(eC 1 ) t d(eC 1 ) t h(eCp0a) t d(p0aCe) address t h(eCbhe) t d(bheCe) t d(aleCe) t w(ale) t d(r/wCe) t h(eCr/w) t d(eCpiq) memory expansion mode and microprocessor mode : when 3- access in high-speed running t h(eCp1a) t d(p1aCe) address t h(eCp1q) t d(p1aCe) data t d(eCp1q) data t h(eCp2q) t d(p2aCe) t d(eCp2q) t d(eCale) t d(p1aCale) t h(aleCp1a) t d(p2aCale) t h(aleCp2a) x in 1 address output a 0 Ca 7 bhe output port pi output (i = 4C8) test conditions (p4Cp8) ?v cc = 5 v10% ?input timing voltage : v il = 1.0 v, v ih = 4.0 v ?output timing voltage : v ol = 0.8 v, v oh = 2.0 v e address output a 8 Ca 15 (byte = h) data input d 8 Cd 15 (byte = l) address/data output a 16 /d 0 Ca 23 /d 7 ale output r/w output data input d 0 Cd 7 address/data output a 8 /d 8 Ca 15 /d 15 (byte = l) test conditions ( 1 , e, p0Cp3) ?v cc = 5 v10% ?output timing voltage : v ol = 0.8 v, v oh = 2.0 v ?data input : v il = 0.8 v, v ih = 2.5 v h) l)
electrical characteristics 7751 group users manual 15C37 15.11 memory expansion mode and microprocessor mode : when 3- f access in high-speed running t w( address t pzx(eCp1z) t d(p1aCe) t d(p1aCe) t w(l) t w(h) t r t f t c t w( t w(el) t d(eC 1 ) t d(eC 1 ) t h(eCp0a) t h(eCp1a) t d(p0aCe) t pxz(eCp1z) address t h(aleCp1a) t d(p1aCale) t h(eCbhe) t h(bheCe) t d(aleCe) t w(ale) t d(r/wCe) t h(eCr/w) t su(pidCe) memory expansion mode and microprocessor mode : when 3- access in high-speed running data t h(eCp1d) t h(eCpid) t d(p2aCe) t pzx(eCp2z) data t su(p2dCe) t h(eCp2d) t su(p1dCe) address x in 1 address output a 0 Ca 7 bhe output port pi output (i = 4C8) test conditions (p4Cp8) ?v cc = 5 v10% ?input timing voltage : v il = 1.0 v, v ih = 4.0 v ?output timing voltage : v ol = 0.8 v, v oh = 2.0 v e address output a 8 Ca 15 (byte = h) data input d 8 Cd 15 (byte = l) address/data output a 16 /d 0 Ca 23 /d 7 ale output r/w output data input d 0 Cd 7 address/data output a 8 /d 8 Ca 15 /d 15 (byte = l) test conditions ( 1 , e, p0Cp3) ?v cc = 5 v10% ?output timing voltage : v ol = 0.8 v, v oh = 2.0 v ?data input : v il = 0.8 v, v ih = 2.5 v t d(eCale) t pxz(eCp2z) t h(aleCp2a) t d(p2aCale) t su(p0a/p1a/p2aCp1d/p2d) address l) h)
electrical characteristics 7751 group users manual 15C38 15.12 memory expansion mode and microprocessor mode : when 4- f access in high-speed running 15.12 memory expansion mode and microprocessor mode : when 4- f access in high-speed running timing requirements (v cc = 5 v 10%, v ss = 0 v, ta = C20 to 85 c, f(x in ) = 40 mhz, unless otherwise noted) ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns limits min. max. unit symbol parameter data formula (max.) 8 8 25 t c /2C8 t c /2C8 30 30 60 60 60 60 60 0 0 0 0 0 0 0 100 7 5 10 9 f(x in ) C75 external clock input cycle time external clock input high-level pulse width external clock input low-level pulse width external clock rise time external clock fall time port p1 input setup time port p2 input setup time port p4 input setup time port p5 input setup time port p6 input setup time port p7 input setup time port p8 input setup time port p1 input hold time port p2 input hold time port p4 input hold time port p5 input hold time port p6 input hold time port p7 input hold time port p8 input hold time port pi data setup time with address stabilized t c t w(h) t w(l) t r t f t su(p1dCe) t su(p2dCe) t su(p4dCe) t su(p5dCe) t su(p6dCe) t su(p7dCe) t su(p8dCe) t h(eCp1d) t h(eCp2d) t h(eCp4d) t h(eCp5d) t h(eCp6d) t h(eCp7d) t h(eCp8d) t su(p0a/p1a/p2aCp1d/p2d)
electrical characteristics 7751 group users manual 15C39 switching characteristics (v cc = 5 v 10%, v ss = 0 v, ta = C20 to 85 c, f(x in ) = 40 mhz, unless otherwise noted) ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns limits min. max. unit symbol parameter data formula (min.) port p4 data output delay time port p5 data output delay time port p6 data output delay time port p7 data output delay time port p8 data output delay time f high-level pulse width f low-level pulse width f 1 output delay time _ e low-level pulse width port p0 address output delay time port p1 data output delay time (byte = l) port p1 floating start delay time (byte = l) port p1 address output delay time port p1 address output delay time port p2 data output delay time port p2 floating start delay time port p2 address output delay time port p2 address output delay time ale output delay time ale output delay time ale pulse width ____ bhe output delay time __ r/w output delay time 60 60 60 60 60 18 35 5 35 5 5 5 0 75 40 40 30 40 30 10 5 35 45 45 C 30 C 30 C 15 3 5 10 9 f(x in ) 3 5 10 9 f(x in ) 2 5 10 9 f(x in ) C 15 1 5 10 9 f(x in ) C 20 2 5 10 9 f(x in ) C 35 3 5 10 9 f(x in ) C 20 2 5 10 9 f(x in ) C 35 3 5 10 9 f(x in ) C 35 3 5 10 9 f(x in ) C 25 4 5 10 9 f(x in ) C 20 1 5 10 9 f(x in ) C 20 1 5 10 9 f(x in ) note: for test conditions, refer to figure 15.15.1. 15.12 memory expansion mode and microprocessor mode : when 4- f access in high-speed running 1 5 10 9 2 5 f(x in ) C 7.5 t d(eCp4q) t d(eCp5q) t d(eCp6q) t d(eCp7q) t d(eCp8q) t w( f h) t w( f l) t d(eC f 1 ) t w(el) t d(p0aCe) t d(eCp1q) t pxz(eCp1z) t d(p1aCe) t d(p1aCale) t d(eCp2q) t pxz(eCp2z) t d(p2aCe) t d(p2aCale) t d(eCale) t d(aleCe) t w(ale) t d(bheCe) t d(r/wCe)
electrical characteristics 7751 group users manual 15C40 15.12 memory expansion mode and microprocessor mode : when 4- f access in high-speed running switching characteristics (v cc = 5 v 10%, v ss = 0 v, ta = C20 to 85 c, f(x in ) = 40 mhz, unless otherwise noted) ns ns ns ns ns ns ns ns ns ns limits min. max. unit symbol parameter data formula (min.) 15 10 15 15 15 10 15 15 15 15 port p0 address hold time port p1 address hold time (byte = l) port p1 data hold time (byte = l) port p1 floating release delay time (byte = l) port p1 address hold time (byte = h) port p2 address hold time port p2 data hold time port p2 floating release delay time ____ bhe hold time __ r/w hold time C 10 1 5 10 9 f(x in ) C 10 1 5 10 9 f(x in ) C 10 1 5 10 9 f(x in ) C 10 1 5 10 9 f(x in ) C 10 1 5 10 9 f(x in ) C 10 1 5 10 9 f(x in ) C 10 1 5 10 9 f(x in ) C 10 1 5 10 9 f(x in ) note: for test conditions, refer to figure 15.15.1. C 15 1 5 10 9 f(x in ) C 15 1 5 10 9 f(x in ) t h(eCp0a) t h(aleCp1a) t h(eCp1q) t pzx(eCp1z) t h(eCp1a) t h(aleCp2a) t h(eCp2q) t pzx(eCp2z) t h(eCbhe) t h(eCrw)
electrical characteristics 7751 group users manual 15C41 15.12 memory expansion mode and microprocessor mode : when 4- f access in high-speed running t w( address t d(p1aCe) t d(p1aCe) t d(p0aCe) t w(l) t w(h) t r t f t c t w( t w(el) t d(eC 1 ) t d(eC 1 ) t h(eCp0a) t h(eCp1a) t h(eCp1q) t d(eCp1q) address address data t h(eCp2q) t d(eCp2q) data t h(aleCp1a) t d(p1aCale) t h(aleCp2a) t d(p2aCale) t h(eCbhe) t d(bheCe) t w(ale) t d(aleCe) t d(r/wCe) t h(eCr/w) t d(eCpiq) memory expansion mode and microprocessor mode : when 4- access in high-speed running t d(eCale) t d(p2aCe) address x in 1 address output a 0 Ca 7 bhe output port pi output (i = 4C8) test conditions (p4Cp8) ?v cc = 5 v10% ?input timing voltage : v il = 1.0 v, v ih = 4.0 v ?output timing voltage : v ol = 0.8 v, v oh = 2.0 v e address output a 8 Ca 15 (byte = h) data input d 8 Cd 15 (byte = l) address/data output a 16 /d 0 Ca 23 /d 7 ale output r/w output data input d 0 Cd 7 address/data output a 8 /d 8 Ca 15 /d 15 (byte = l) test conditions ( 1 , e, p0Cp3) ?v cc = 5 v10% ?output timing voltage : v ol = 0.8 v, v oh = 2.0 v ?data input : v il = 0.8 v, v ih = 2.5 v l) h)
electrical characteristics 7751 group users manual 15C42 15.12 memory expansion mode and microprocessor mode : when 4- f access in high-speed running t w( t d(p1aCe) t d(p1aCe) t w(l) t w(h) t r t f t c t w( t w(el) t d(eC 1 ) t d(eC 1 ) t h(eCp0a) t h(eCp1a) t d(p0aCe) t pzx(eCp1z) t pxz(eCp1z) address address address t h(aleCp1a) t d(p1aCale) t h(eCbhe) t d(bheCe) t d(aleCe) t d(eCale) t w(ale) t d(r/wCe) t h(eCr/w) t su(pidCe) memory expansion mode and microprocessor mode : when 4- access in high-speed running data t su(p1dCe) t h(eCp1d) t h(eCpid) t d(p2aCe) t pzx(eCp2z) data t su(p2dCe) t h(eCp2d) x in 1 address output a 0 Ca 7 bhe output port pi output (i = 4C8) test conditions (p4Cp8) ?v cc = 5 v10% ?input timing voltage : v il = 1.0 v, v ih = 4.0 v ?output timing voltage : v ol = 0.8 v, v oh = 2.0 v e address output a 8 Ca 15 (byte = h) data input d 8 Cd 15 (byte = l) address/data output a 16 /d 0 Ca 23 /d 7 ale output r/w output data input d 0 Cd 7 address/data output a 8 /d 8 Ca 15 /d 15 (byte = l) test conditions ( 1 , e, p0Cp3) ?v cc = 5 v10% ?output timing voltage : v ol = 0.8 v, v oh = 2.0 v ?data input : v il = 0.8 v, v ih = 2.5 v t h(aleCp2a) t pxz(eCp2z) t d(p2aCale) t su(p0a/p1a/p2aCp1d/p2d) address l) h)
electrical characteristics 7751 group users manual 15C43 15.13 memory expansion mode and microprocessor mode : when 5- f access in high-speed running 15.13 memory expansion mode and microprocessor mode : when 5- f access in high-speed running timing requirements (v cc = 5 v 10%, v ss = 0 v, ta = C20 to 85 c, f(x in ) = 40 mhz, unless otherwise noted) ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns limits min. max. unit symbol parameter data formula (max.) 8 8 25 t c /2C8 t c /2C8 30 30 60 60 60 60 60 0 0 0 0 0 0 0 150 9 5 10 9 f(x in ) C75 external clock input cycle time external clock input high-level pulse width external clock input low-level pulse width external clock rise time external clock fall time port p1 input setup time port p2 input setup time port p4 input setup time port p5 input setup time port p6 input setup time port p7 input setup time port p8 input setup time port p1 input hold time port p2 input hold time port p4 input hold time port p5 input hold time port p6 input hold time port p7 input hold time port p8 input hold time port pi data setup time with address stabilized t c t w(h) t w(l) t r t f t su(p1dCe) t su(p2dCe) t su(p4dCe) t su(p5dCe) t su(p6dCe) t su(p7dCe) t su(p8dCe) t h(eCp1d) t h(eCp2d) t h(eCp4d) t h(eCp5d) t h(eCp6d) t h(eCp7d) t h(eCp8d) t su(p0a/p1a/p2aCp1d/p2d)
electrical characteristics 7751 group users manual 15C44 15.13 memory expansion mode and microprocessor mode : when 5- f access in high-speed running switching characteristics (v cc = 5 v 10%, v ss = 0 v, ta = C20 to 85 c, f(x in ) = 40 mhz, unless otherwise noted) t d(eCp4q) t d(eCp5q) t d(eCp6q) t d(eCp7q) t d(eCp8q) t w( f h) t w( f l) t d(eC f 1 ) t w(el) t d(p0aCe) t d(eCp1q) t pxz(eCp1z) t d(p1aCe) t d(p1aCale) t d(eCp2q) t pxz(eCp2z) t d(p2aCe) t d(p2aCale) t d(eCale) t d(aleCe) t w(ale) t d(bheCe) t d(r/wCe) ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns limits min. max. unit symbol parameter data formula (min.) port p4 data output delay time port p5 data output delay time port p6 data output delay time port p7 data output delay time port p8 data output delay time f high-level pulse width f low-level pulse width f 1 output delay time _ e low-level pulse width port p0 address output delay time port p1 data output delay time (byte = l) port p1 floating start delay time (byte = l) port p1 address output delay time port p1 address output delay time port p2 data output delay time port p2 floating start delay time port p2 address output delay time port p2 address output delay time ale output delay time ale output delay time ale pulse width ____ bhe output delay time __ r/w output delay time 60 60 60 60 60 18 35 5 35 5 5 5 0 125 40 40 30 40 30 10 5 35 45 45 C 30 C 30 C 15 3 5 10 9 f(x in ) 3 5 10 9 f(x in ) 2 5 10 9 f(x in ) C 15 1 5 10 9 f(x in ) C 20 2 5 10 9 f(x in ) C 35 3 5 10 9 f(x in ) C 20 2 5 10 9 f(x in ) C 35 3 5 10 9 f(x in ) C 35 3 5 10 9 f(x in ) C 25 6 5 10 9 f(x in ) C 20 1 5 10 9 f(x in ) C 20 1 5 10 9 f(x in ) note: for test conditions, refer to figure 15.15.1. 1 5 10 9 2 5 f(x in ) C 7.5
electrical characteristics 7751 group users manual 15C45 15.13 memory expansion mode and microprocessor mode : when 5- f access in high-speed running switching characteristics (v cc = 5 v 10%, v ss = 0 v, ta = C20 to 85 c, f(x in ) = 40 mhz, unless otherwise noted) ns ns ns ns ns ns ns ns ns ns limits min. max. unit symbol parameter data formula (min.) 15 10 15 15 15 10 15 15 15 15 port p0 address hold time port p1 address hold time (byte = l) port p1 data hold time (byte = l) port p1 floating release delay time (byte = l) port p1 address hold time (byte = h) port p2 address hold time port p2 data hold time port p2 floating release delay time ____ bhe hold time __ r/w hold time C 10 1 5 10 9 f(x in ) C 10 1 5 10 9 f(x in ) C 10 1 5 10 9 f(x in ) C 10 1 5 10 9 f(x in ) C 10 1 5 10 9 f(x in ) C 10 1 5 10 9 f(x in ) C 10 1 5 10 9 f(x in ) C 10 1 5 10 9 f(x in ) note: for test conditions, refer to figure 15.15.1. C 15 1 5 10 9 f(x in ) C 15 1 5 10 9 f(x in ) t h(eCp0a) t h(aleCp1a) t h(eCp1q) t pzx(eCp1z) t h(eCp1a) t h(aleCp2a) t h(eCp2q) t pzx(eCp2z) t h(eCbhe) t h(eCrw)
electrical characteristics 7751 group users manual 15C46 15.13 memory expansion mode and microprocessor mode : when 5- f access in high-speed running address t w( t w( t d(eC 1 ) memory expansion mode and microprocessor mode : when 5- access in high-speed running t d(p0aCe) t w(h) t w(l) t f t r t c address t d(eC 1 ) t w(el) t h(eCp0a) t d(p1aCe) address t h(eCp1a) t d(p1aCe) data t h(eCp1q) data t d(eCp1q) t d(p2aCe) data t h(eCp2q) t d(eCp2q) t h(aleCp1a) t h(aleCp2a) t d(p1aCale) t d(p2aCale) t d(r/wCe) t d(bheCe) t d(eCale) t w(ale) t d(aleCe) t h(eCbhe) t h(eCr/w) t d(eCpiq) x in 1 address output a 0 Ca 7 bhe output port pi output (i = 4C8) test conditions (p4Cp8) ?v cc = 5 v10% ?input timing voltage : v il = 1.0 v, v ih = 4.0 v ?output timing voltage : v ol = 0.8 v, v oh = 2.0 v e address output a 8 Ca 15 (byte = h) data input d 8 Cd 15 (byte = l) address/data output a 16 /d 0 Ca 23 /d 7 ale output r/w output data input d 0 Cd 7 address/data output a 8 /d 8 Ca 15 /d 15 (byte = l) test conditions ( 1 , e, p0Cp3) ?v cc = 5 v10% ?output timing voltage : v ol = 0.8 v, v oh = 2.0 v ?data input : v il = 0.8 v, v ih = 2.5 v l) h)
electrical characteristics 7751 group users manual 15C47 15.13 memory expansion mode and microprocessor mode : when 5- f access in high-speed running t su(pi dCe) t d(p2aCe) t pzx(eCp2z) address t pxz(eCp2z) t h(aleCp2a) data t h(eCp2d) t su(p2dCe) t w( t w( t d(eC 1 ) memory expansion mode and microprocessor mode : when 5- access in high-speed running t d(p0aCe) t w(h) t w(l) t f t r t c address t d(eC 1 ) t w(el) t d(p1aCe) t d(p1aCe) t h(eCp1a) t h(eCp0a) t pzx(eCp1z) address address t pxz(eCp1z) t h(aleCp1a) t d(p1aCale) t d(r/wCe) t d(bheCe) t d(eCale) t w(ale) t d(aleCe) t h(eCbhe) t h(eCpid ) data t h(eCp1d) t su(p1dCe) t h(eCr/w) x in 1 address output a 0 Ca 7 bhe output port pi output (i = 4C8) test conditions (p4Cp8) ?v cc = 5 v10% ?input timing voltage : v il = 1.0 v, v ih = 4.0 v ?output timing voltage : v ol = 0.8 v, v oh = 2.0 v e address output a 8 Ca 15 (byte = h) data input d 8 Cd 15 (byte = l) address/data output a 16 /d 0 Ca 23 /d 7 ale output r/w output data input d 0 Cd 7 address/data output a 8 /d 8 Ca 15 /d 15 (byte = l) test conditions ( 1 , e, p0Cp3) ?v cc = 5 v10% ?output timing voltage : v ol = 0.8 v, v oh = 2.0 v ?data input : v il = 0.8 v, v ih = 2.5 v t d(p2aCale) t su(p0a/p1a/p2aCp1d/p2d) l) h)
electrical characteristics 7751 group users manual 15C48 15.14 memory expansion mode and microprocessor mode : when 2- f access in high-speed running (internal ram access) 15.14 memory expansion mode and microprocessor mode : when 2- f access in high-speed running (internal ram access) timing requirements (v cc = 5 v10%, v ss = 0 v, ta = C20 to 85 c, f(x in ) = 40 mhz, unless otherwise noted) ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns limits min. max. unit symbol parameter data formula (min.) f high-level pulse width f low-level pulse width f 1 output delay time _ e low-level pulse width port p0 address output delay time port p1 floating start delay time (byte = l) port p1 address output delay time port p1 address output delay time port p2 floating start delay time port p2 address output delay time port p2 address output delay time ale output delay time ale output delay time ale pulse width ____ bhe output delay time __ r/w output delay time port p0 address hold time port p1 address hold time (byte = l) port p1 floating release delay time (byte = l) port p1 address hold time (byte = h) port p2 address hold time port p2 floating release delay time ____ bhe hold time __ r/w hold time 18 5 5 2 5 10 9 f(x in ) C 20 1 5 10 9 f(x in ) C 20 1 5 10 9 f(x in ) C 20 1 5 10 9 f(x in ) C 35 C 20 1 5 10 9 f(x in ) C 35 2 5 10 9 f(x in ) 5 5 0 5 15 15 5 15 5 10 5 10 20 20 15 10 15 15 10 15 15 15 C 20 1 5 10 9 f(x in ) C 35 2 5 10 9 f(x in ) 1 5 10 9 2 5 f(x in ) C 30 C 30 C 15 2 5 10 9 f(x in ) 2 5 10 9 f(x in ) 1 5 10 9 f(x in ) C 15 1 5 10 9 f(x in ) C 7.5 C 10 1 5 10 9 f(x in ) C 10 1 5 10 9 f(x in ) C 15 1 5 10 9 f(x in ) C 10 1 5 10 9 f(x in ) C 15 1 5 10 9 f(x in ) C 10 1 5 10 9 f(x in ) C 10 1 5 10 9 f(x in ) C 10 1 5 10 9 f(x in ) t w( f h) t w( f l) t d(eC f 1 ) t w(el) t d(p0aCe) t pxz(eCp1z) t d(p1aCe) t d(p1aCale) t pxz(eCp2z) t d(p2aCe) t d(p2aCale) t d(eCale) t d(aleCe) t w(ale) t d(bheCe) t d(r/wCe) t h(eCp0a) t h(aleCp1a) t pzx(eCp1z) t h(eCp1a) t h(aleCp2a) t pzx(eCp2z) t h(eCbhe) t h(eCr/w)
electrical characteristics 7751 group users manual 15C49 15.14 memory expansion mode and microprocessor mode : when 2- f access in high-speed running (internal ram access) t w(el) t w( t h(aleCp1a) data t d(r/wCe) t w(ale) t h(eCr/w) t h(eCp0a) t h(eCp1a) t d(p1aCe) t d(p1aCe) t w(l) t w(h) t r t f t c t w( t d(eC 1 ) t d(eC 1 ) t d(p0aCe) t d(p2aCe) t d(p1aCale) t h(aleCp2a) t d(p2aCale) t h(eCbhe) t d(bheCe) t d(aleCe) t d(eCale) memory expansion mode and microprocessor mode : when 2- access in high-speed running (internal ram access) ] the undefined value is output. address x in 1 address output a 0 Ca 7 bhe output e address output a 8 Ca 15 (byte = h) data input d 8 Cd 15 (byte = l) address/data output a 16 /d 0 Ca 23 /d 7 ale output r/w output data input d 0 Cd 7 address/data output a 8 /d 8 Ca 15 /d 15 (byte = l) test conditions ( 1 , e, p0Cp3) ?v cc = 5 v10% ?output timing voltage : v ol = 0.8 v, v oh = 2.0 v ?data input : v il = 0.8 v, v ih = 2.5 v ] data ] l) h)
electrical characteristics 7751 group users manual 15C50 15.14 memory expansion mode and microprocessor mode : when 2- f access in high-speed running (internal ram access) t w(el) t h(eCp0a) address address t d(aleCe) t d(p2aCe) t d(p2aCale) t w( t w( t d(eC 1 ) memory expansion mode and microprocessor mode : when 2- access in high-speed running (internal ram access) t d(p0aCe) t w(h) t w(l) t f t r t c t d(eC 1 ) t d(p1aCe) t d(p1aCe) t h(eCp1a) address t d(p1aCale) t d(bheCe) t h(eCbhe) t d(r/wCe) t w(ale) t h(eCr/w) t pzx(eCp1z) address t pzx(eCp2z) ] the contents of external data bus cannot be read into the internal. x in 1 address output a 0 Ca 7 bhe output e address output a 8 Ca 15 (byte = h) data input d 8 Cd 15 (byte = l) address/data output a 16 /d 0 Ca 23 /d 7 ale output r/w output data input d 0 Cd 7 address/data output a 8 /d 8 Ca 15 /d 15 (byte = l) test conditions ( 1 , e, p0Cp3) ?v cc = 5 v10% ?output timing voltage : v ol = 0.8 v, v oh = 2.0 v ?data input : v il = 0.8 v, v ih = 2.5 v t pxz(eCp1z) t h(aleCp1a) t pxz(eCp2z) t h(aleCp2a) t d(eCale) l) h)
electrical characteristics 7751 group users manual 15C51 _ 15.15 testing circuit for ports p0 to p8, f 1 , and e _ 15.15 testing circuit for ports p0 to p8, f 1 , and e _ fig. 15.15.1 testing circuit for ports p0 to p8, f 1 , and e p0 p1 p2 p3 p4 p5 p6 p7 p8 100pf 1 e
electrical characteristics 7751 group users manual 15C52 memorandum 15.15 testing circuit for ports p0 to p8, f 1 , and e
chapter 16 standard characteristics 16.1 standard characteristics
st andard characteristics 16.1 standard characteristics 7751 group users manual 16C2 16.1 standard characteristics standard characteristics described below are just examples of the m37751m6c-xxxfps characteristics and are not guaranteed. for rated values, refer to chapter 15. electrical characteristics. 16.1.1 programmable i/o port (cmos output) standard characteristics (1) p-channel i oh Cv oh characteristics 0 5.0 40.0 10.0 20.0 30.0 1.0 2.0 3.0 4.0 v oh [v] i oh [ma] t a = 25 c t a = 85 c 0 5.0 40.0 10.0 20.0 30.0 1.0 2.0 3.0 4.0 v ol [v] i ol [ma] t a = 25 c t a = 85 c (2) n-channel i ol Cv ol characteristics
st andard characteristics 16.1 standard characteristics 7751 group users manual 16C3 16.1.2 iccCf(x in ) standard characteristics (1) iccCf(x in ) standard characteristics on operating and at reset measuring conditions (v cc = 5.0 v, t a = 25 c, f(x in ) ; square waveform) 0 10 20 30 40 10 20 f(x in ) [mhz] i cc [ma] on operating in single-chip mode at reset (2) iccCf(x in ) standard characteristics during wait mode measuring conditions (v cc = 5.0 v, t a = 25 c, f(x in ) ; square waveform) 0 10 20 30 40 2 4 f(x in ) [mhz] i cc [ma] 1 3 5 6 in single-chip mode
st andard characteristics 16.1 standard characteristics 7751 group users manual 16C4 16.1.3 a-d converter standard characteristics the lower line of the graph indicates the absolute precision errors. these are expressed as the deviation from the ideal value when the output code changes. for example, the change in output code from 15 to 16 should occurs at 77.5 mv, but the measured value is C1.2 mv. accordingly, the measured point of change is 77.5 C 1.2 = 76.3 mv. the upper line of the graph indicates the input voltage width for which the output code is constant. for example, the measured input voltage width for which the output code is 16 is 4.9 mv, so that the differential non-linear error is 4.9 C 5 = C0.1 mv (C0.02 lsb).
standard characteristics 16.1 standard characteristics 7751 group users manual 16C5 [measuring conditions] ?vcc = 5.12 v, ?v ref = 5.12 v, ?f(x in ) = 40 mhz, ?ta = 25 c
st andard characteristics 16.1 standard characteristics 7751 group users manual 16C6 memorandum
chapter 17 applications 17.1 memory expansion
applications 7751 group users manual 17C2 17.1 memory expansion 17.1 memory expansion this section shows examples for memory and i/o expansion. refer to chapter 12. connection with external devices for details about the functions and operation of used pins when expanding a memory or i/o. refer to chapter 15. electrical characteristics for timing requirements of the microcomputer. application shown here are just examples. the user shall modify them according to the actual application and test them. 17.1.1 memory expansion model memory expansion to the external is possible in the memory expansion mode or the microprocessor mode. the level of the external data bus width select signal makes it possible to select the four memory expansion models shown in table 17.1.1. (1) minimum model this is an expansion model of which external data bus width is 8 bits and accessible area is expanded up to 64 kbytes. it is unnecessary to connect the address latch externally. this is an expansion model which is suited to having priority the cost when connecting the memory of which external data bus width is 8 bits. (2) medium model a this is an expansion model of which external data bus width is 8 bits and accessible area is expanded up to 16 mbytes. in this expansion model, the high-order 8 bits of the external address bus (a 23 to a 16 ) are multiplexed with the external data bus. therefore, an n-bit (n 8) address latch is required for latching address (n bits of a 23 to a 16 ). (3) medium model b this is an expansion model of which external data bus width is 16 bits and accessible area is expanded up to 64 kbytes. this expansion model is used when having priority the rate performance. in this expansion model, the middle-order 8 bits of the external address bus (a 15 to a 8 ) are multiplexed with the external data bus. therefore, an 8-bit address latch is required for latching address (a 15 to a 8 ). (4) maximum model this is an expansion model of which external data bus width is 16 bits and accessible area is expanded up to 16 mbytes. in this expansion model, the high- and middle-order 16 bits of the external address bus (a 23 to a 8 ) are multiplexed with the external data bus. therefore, an 8-bit address latch for latching a 15 to a 8 and an n-bit (n 8) address latch for latching n bits of a 23 to a 16 are required.
applications 7751 group users manual 17C3 17.1 memory expansion table 17.1.1 memory expansion model byte byte m37751 byte m37751 byte m37751 a 0 Ca 15 16 d 0 Cd 7 8 a 0 Ca 15 e d 0 Cd 15 8 16 16 dq a 0 Ca 15+n d 0 Cd 7 8 16+n e n dq latch e a 0 Ca 15+n d 0 Cd 15 8 16 n 16+n dq e dq p0 p1 p2 ale bhe m37751 p0 p1 p2 p0 p1 p2 ale ale bhe p0 p1 p2 8-bit width; byte = h notes 1 : refer to chapter 12. connection with external devices for details about the functions and operation of used pins when expanding a memory. refer to chapter 15. electrical characteristics for timing requirements. 2 : because the address bus width is used as maximum 24 bits when expanding a memory, strengthen the m37751s vss line. (refer to appendix 8. examples of noise immunity improvement. ) external data bus width 16-bit width; byte = l access area maximum 64 kbytes maximum 16 mbytes memory expansion model minimum model latch memory expansion model medium model b memory expansion model medium model a latch latch memory expansion model maximum model
applications 7751 group users manual 17C4 17.1 memory expansion 17.1.2 how to calculate timing when expanding a memory, use a memory of which standard specifications satisfy the address access time and the data setup time for write. the following describes how to calculate each timing. external memorys address access time; t a(ad) t a(ad) = t su(p0a/p1a/p2a-p1d/p2d) C (address decode time ] 1 + address latch delay time ] 2 ) address decode time ] 1 : time required for the chip select signal to be enabled after decoding address address latch delay time ] 2 : delay time required when latching address (unnecessary in minimum model) external memorys data setup time for write; t su(d) t su(d) = t w(el) C t d(eCp2q/p1q) t d(eCp2q/p1q) : t d(eCp2q) or t d(eCp1q) table 17.1.2 lists the data or the calculation formulas for each parameter. figure 17.1.1 shows the bus timing diagram. figures 17.1.2 and 17.1.4 show the relationship between t su(p0a/p1a/p2a-p1d/p2d) and f(x in ); figures 17.1.3 and 17.1.5 show the relationship between t su(d) and f(x in ). table 17.1.2 data or calculation formulas for each parameter (unit: ns) parameter bus cycle low-speed running 2 f access low-speed running 3 f access low-speed running 4 f access high-speed running 3 f access high-speed running 4 f access high-speed running 5 f access C 65 3 5 10 9 f(x in ) t su(p0a/p1a/p2a p1d/p2d) t w(el) t d(e-p2q) t d(e-p1q) C 65 5 5 10 9 f(x in ) C 65 7 5 10 9 f(x in ) C 75 5 5 10 9 f(x in ) C 75 7 5 10 9 f(x in ) C 75 9 5 10 9 f(x in ) C 25 4 5 10 9 f(x in ) C 25 3 5 10 9 f(x in ) C 25 C 25 4 5 10 9 f(x in ) C 25 4 5 10 9 f(x in ) 6 5 10 9 f(x in ) C 25 2 5 10 9 f(x in ) 35 35 35 35 35 35
applications 7751 group users manual 17C5 17.1 memory expansion fig. 17.1.1 bus timing diagrams e ale t su(p0a/p1a/p2a-p1d/p2d) t w(el) t d(e-p2q) t d(e-p1q) r/w e ale address low-order t su(p0a/p1a/p2aCp1d/p2d) t w(el) port p0 (a 0 Ca 7 ) port p1 (a 8 Ca 15 ) port p2 (a 16 /d 0 Ca 23 /d 7 ) t d(e-p2q) r/w t a(ad) t su(d) t w(el) t a(ad) t su(d) t w(el) : specifications of the m37751 (the others are the external memorys.) external data bus width = 8 bits (byte = h) external data bus width = 16 bits (byte = l) external memory output data data address low-order address middle-order address middle-order address high-order address high-order when writing data when reading data when writing data when reading data data (even address) address middle-order data (odd address) address middle-order address high-order address high-order address low-order address low-order port p0 (a 0 Ca 7 ) port p1 (a 8 /d 8 Ca 15 /d 15 ) port p2 (a 16 /d 0 Ca 23 /d 7 ) external memory output data external memory output data
applications 7751 group users manual 17C6 17.1 memory expansion fig. 17.1.2 relationship between t su(p0a/p1a/p2a-p1d/p2d) and f(x in ) (at low-speed running) fig. 17.1.3 relationship between t su(d) and f(x in ) (at low-speed running) 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 0 100 200 300 400 500 600 700 800 900 1000 935 649 162 152 143 135 363 165 149 135 122 111 101 92 85 77 71 65 60 55 810 712 635 571 518 473 435 401 372 346 323 303 285 268 253 239 226 215 560 490 435 389 351 319 292 268 247 229 212 198 185 173 310 268 235 207 185 operation clock frequency f(x in ) [mhz] [ns] port pi data setup time with address stabilized t su (p0a/p1a/p2aCp1d/p2d) 4 access in low-speed running 3 access in low-speed running 2 access in low-speed running 7 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 [mhz] [ns] data setup time for writing to external memory t su (d) 511 440 384 340 303 273 247 225 206 190 175 162 150 140 130 121 113 106 100 57 225 190 162 140 121 106 93 82 65 51 45 40 35 30 26 23 20 73 0 100 200 300 400 500 600 operation clock frequency f(x in ) 3 access in low-speed running or 4 access in low-speed running 2 access in low-speed running 8
applications 7751 group users manual 17C7 17.1 memory expansion fig. 17.1.4 relationship between t su(p0a/p1a/p2aCp1d/p2d) and f(x in ) (at high-speed running) fig. 17.1.5 relationship between t su(d) and f(x in ) (at high-speed running) 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 0 50 100 150 200 250 300 350 334 316 300 285 271 258 246 235 225 215 206 197 189 182 175 168 161 155 150 243 229 216 205 194 184 175 166 158 150 143 137 130 125 119 114 109 104 100 152 142 133 125 117 110 103 97 91 86 81 76 72 67 63 60 56 53 50 [mhz] [ns] operation clock frequency f(x in ) port pi data setup time with address stabilized t su (p0a/p1a/p2aCp1d/p2d) 5 access in high-speed running 4 access in high-speed running 3 access in high-speed running 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 220 0 20 40 60 80 100 120 140 160 180 200 212 200 190 180 170 162 154 146 140 133 127 121 116 111 106 102 97 93 90 [mhz] [ns] 76 70 65 55 51 47 43 40 36 33 30 28 25 23 21 18 16 15 60 121 113 106 100 93 88 82 77 73 69 65 61 57 54 51 48 45 42 40 data setup time for writing to external memory t su (d) operation clock frequency f(x in ) 5 access in high-speed running 4 access in high-speed running 3 access in high-speed running
applications 7751 group users manual 17C8 17.1 memory expansion 17.1.3 points in memory expansion (1) reading data figure 17.1.6 shows the timing at which data is read from an external memory. when reading data, the external data bus is placed in a floating state, and data is read from the _ external memory. this floating state is maintained from t pxz(eCp1z/p2z) after falling of the e signal till _ t pzx(eCp1z/p2z) after rising of the e signal. table 17.1.3 lists the values of t pxz(eCp1z/p2z) and the formulas to calculate t pzx(eCp1z/p2z) . consider timing during data read to avoid collision between the data being readCin and the preceding or following address output because the external data bus is multiplexed with the external address bus. (refer to (3) precautions on memory expansion. ) fig. 17.1.6 timing at which data is read from external memory external memory dat a out put ] 1: this applies when the external data bus has a width of 16 bits (byte = l). external memory output enable signal (read signal) oe e external memory chip select signal ce, s ] 2: if one of the external memorys specifications is smaller than t pxz (e-p1z/p2z) , there is a possibility of the tail of ? refer to (3) precautions on memory expansion. ] 3: if one of the external memorys specifications is greater than t pzx (e-p1z/p2z) data colliding with the head of address. ? refer to (3) precautions on memory expansion. address output and data input a 8 / d 8 Ca 15 /d 15 a 16 /d 0 Ca 23 /d 7 ] 1 t en (oe) address t pzx (e-p1z/p2z) t su (p1d/p2d-e) : specifications of the m37751 (the others are the external memorys.) t a (oe) t a (ce) , t a (s) t df , t dis (oe) ] 2 ] 3 t w(el) data t pxz (e-p1z/p2z) t en (ce) , t en (s) address , there is a possibility of the tail of address colliding with the head of data .
applications 7751 group users manual 17C9 17.1 memory expansion table 17.1.3 values of t pxz(eCp1z/p2z) and formulas to calculate t pzx(eCp1z/p2z) (unit : ns) parameter bus cycle low-speed running 2 f access low-speed running 3 f access low-speed running 4 f access high-speed running 3 f access high-speed running 4 f access high-speed running 5 f access t pxz(ep1z) t pxz(ep2z) t pzx(ep1z) t pzx(ep2z) C 22 1 5 10 9 f(x in ) C 10 C 10 1 5 10 9 f(x in ) 1 5 10 9 f(x in ) C 10 1 5 10 9 f(x in ) 5 5 5 5 5 5 C 22 1 5 10 9 f(x in ) C 22 1 5 10 9 f(x in )
applications 7751 group users manual 17C10 17.1 memory expansion (2) writing data figure 17.1.7 shows the timing at which data is written to an external memory. _ when writing data, the output data is validated after t d(e-p1q/p2q) passes from falling of the e signal. its _ validated data is output continuously until t h(e-p1q/p2q) passes from rising of the e signal. table 17.1.4 lists the data of t d(e-p1q/p2q) and the calculation formulas of t h(e-p1q/p2q) . data output at writing data must satisfy the data set up time, t su(d) , and the data hold time, t h(d) , for write to an external memory. fig. 17.1.7 timing at which data is written to external memory table 17.1.4 data of t d(e-p1q/p2q) and calculation formulas of t h(e-p1q/p2q) (unit: ns) parameter bus cycle low-speed running 2 f access low-speed running 3 f access low-speed running 4 f access high-speed running 3 f access high-speed running 4 f access high-speed running 5 f access t d(ep1q) t d(ep2q) t h(ep1q) t hep2q) C 22 1 5 10 9 f(x in ) C 10 C 10 1 5 10 9 f(x in ) 1 5 10 9 f(x in ) C 10 1 5 10 9 f(x in ) 35 35 35 35 35 35 C 22 1 5 10 9 f(x in ) C 22 1 5 10 9 f(x in ) t su (d) t h (d) address data e w, we external memory chip select signals ce, s t w(el) t h (e-p1q/p2q) (the others are the external memorys.) : specifications of the m37751 ] this applies when the external data bus has a width of 16 bits (byte = l). t d (e-p1q/p2q) a 8 /d 8 ea 15 /d 15 a 16 /d 0 ea 23 /d 7 ] address and data output external memory write signals address
applications 7751 group users manual 17C11 17.1 memory expansion (3) precautions on memory expansion as described in to a below, if specifications of the external memory do not match those of the m37751, some considerations must be incorporated into circuit design as in the following cases: when using an external memory that requires a long access time, t a(ad) _ when using an external memory that outputs data within t pxz(e-p1z/p2z) after falling of the e signal _ a when using an external memory that outputs data for more than t pzx(e-p1z/p2z) after rising of the e signal when using an external memory that requires a long access time, t a(ad) if the m37751s t su(p1d/p2d-e) cannot be satisfied because the external memory requires a long access time, t a(ad) , examine the method described below: l lower f(x in ). l select a long bus cycle by software. (refer to section 12.2 bus cycle. ) l use ready function. (refer to section 12.3 ready function. ) figure 17.1.8 shows an example of using ready function (at 2 f access in lowCspeed running ). figure 17.1.9 shows an example of using ready function (at 3 f access in lowCspeed running ). figure 17.1.10 shows an example of using ready function (at 3 f access in highCspeed running ). figure 17.1.11 shows an example of using ready function (at 4 f access in highCspeed running ). ready function is available for the internal areas, so that the circuit in figures 17.1.8 to 17.1.11 ___ use the chip select signal (cs 2 ) to specify the area where ready function is available.
applications 7751 group users manual 17C12 17.1 memory expansion fig. 17.1.8 example of using ready function (at 2 f access in lowCspeed running) m37751 cs 1 a 8 Ca 23 (d 0 Cd 15 ) a 0 Ca 7 ac74 d t q 1 rdy e ac32 ac04 address bus data bus cs 2 address latch circuit address decode circuit circuit condition: f(x in ) 25 mhz, 2 access in low-speed running ready function is available only for areas accessed by cs 2 . sum of propagation delay time for ac32 , ac74, and ac04(max. : 26 ns) ] 1 ] 2 ] 3 1 ] 1, ] 2 use the elements of which propagation delay time is within 12 ns. e cs 2 rdy t c t d (e- 1 ) t su (rdy- 1 ) t su (rdy- 1 ) b a ready request is accepted at the rdy pin input level judgment timing a . : e ( l level) stop by ready function. ready state release request is accepted at the rdy pin input level judgment timing b . q(ac74) 1 1
applications 7751 group users manual 17C13 17.1 memory expansion fig. 17.1.9 example of using ready function (at 3 f access in lowCspeed running) m37751 1d 1t 1q rdy e ac32 2d 2t 2q clr ac04 ac04 ac74 e cs 2 1q (ac74) rdy 2q (ac74) b a t c t d (e- f 1 ) a 8 Ca 23 (d 0 Cd 15 ) a 0 Ca 7 1 cs 1 address bus data bus address latch circuit address decode circuit cs 2 ] 1 ] 2 ] 3 ] 1 to ] 3 (f(x in ) = 25 mhz, 40 ns). 2 5 10 f(x in ) Ct su (rdyC 1 ) 9 ready function is available only for areas accessed by cs 2 . use the elements of which sum of propagation delay time is within circuit condition: f(x in ) 25 mhz, 3 access in lowCspeed running t su(rdy- 1 ) t su(rdy- 1 ) sum of propagation delay time for ac32 , ac74, and ac04(max. : 26 ns) ready request is accepted at the rdy pin input level judgment timing a . ready state release request is accepted at the rdy pin input level judgment timing b . : e ( l level) stop by ready function. 1 1 1
applications 7751 group users manual 17C14 17.1 memory expansion fig. 17.1.10 example of using ready function (at 3 f access in highCspeed running) b a : e ( l level) stop by ready function. ready request is accepted at the rdy pin input level judgment timing a . ready state release request is accepted at the rdy pin input level judgment timing b . :the condition satisfying t su(rdy- 1 ) 3 40 ns is tc 3 35.25 ns. accordingly, when f(x in ) 28 mhz, this circuit example satisfies t su(rdy- 1 ) 3 40 ns. ] t su (rdy- 1 ) ] t su (rdy- 1 ) ] sum of propagation delay time for bc32 5 2 , ac74, and ac04(max. : 30.5 ns) e 1 cs 2 1q (ac74) rdy 2q (ac74) 1 t d (e- 1 ) t c m37751 rdy e a 8 Ca 23 (d 0 Cd 15 ) 1 a 0 Ca 7 1d 1t 1q bc32 2d 2t 2q ac04 ac74 ] 1 ] 2 ] 3 1 ] 4 cs 1 address bus data bus address latch circuit address decode circuit cs 2 ] 1 to ] 4 ready function is available only for areas accessed by cs 2 . use the elements of which sum of propagation delay time is within 30.5 ns. circuit condition: f(x in ) 28 mhz, 3 access in highCspeed running bc32
applications 7751 group users manual 17C15 17.1 memory expansion fig. 17.1.11 example of using ready function (at 4 f access in highCspeed running) m37751 1d 1t 1q bc32 2d 2t 2q ac04 ac74 ] 1 ] 2 ] 3 ] 4 1 e 1 t su (rdy- 1 ) ] t su (rdy- 1 ) ] b a t d (e- 1 ) t c rdy e cs 2 1q (ac74) rdy 2q (ac74) a 8 Ca 23 (d 0 Cd 15 ) cs 1 address bus data bus address latch circuit address decode circuit cs 2 ] 1 to ] 4 ready function is available only for areas accessed by cs 2 . sum of propagation delay time for bc32 5 2 , ac74, and ac04(max. : 30.5 ns) : e ( l level) stop by ready function. use the elements of which sum of propagation delay time is within 30.5 ns. a 0 Ca 7 ready request is accepted at the rdy pin input level judgment timing a . ready state release request is accepted at the rdy pin input level judgment timing b . the condition satisfying t su(rdy- 1) 3 40 ns is tc 3 35.25 ns. accordingly, when f(x in ) 28 mhz, this circuit example satisfies t su(rdy- 1) 3 40 ns. ] circuit condition: f(x in ) 28 mhz, 4 access in highCspeed running 1 1 bc32
applications 7751 group users manual 17C16 17.1 memory expansion _ when using an external memory that outputs data within t pxz(e-p1z/p2z) after falling of the e signal _ because the external memory outputs data within t pxz(e-p1z/p2z) after falling of the e signal, there will be a possibility of the tail of address colliding with the head of data. in such a case, generate the __ _ memory read signal (oe) with delay only the leading edge of the fall of the e. (refer to figure 17.1.12.) fig. 17.1.12 example of causing to delay data output timing note: satisfy t pxz (e-p1z/p2z) t en (oe) +d. if t en (oe) t pxz (e-p1z/p2z) (= 5 ns), secure a certain time (i.e., d in this diagram) from falling of e to the falling of oe. address output external memory data output t pxz (e-p1z/p2z) e oe d address t a (oe) t en (oe) external memory output enable signal (read signal) (the others are the external memorys.) : specifications of the m37751 address data
applications 7751 group users manual 17C17 17.1 memory expansion memory eprom one-time prom flash memory sram _ a when using external memory that outputs data for more than t pzx(e-p1z/p2z) after rising of e signal _ because the external memory outputs data for more than t pzx(e-p1z/p2z) after rising of the e signal, there will be a possibility of the tail of data colliding with the head of address. in such a case, examine the method described below: l cut the tail of data output from the external memory by using, for example, a bus buffer. l use the mitsubishis memory chips that can be connected without a bus buffer. figures 17.1.13 to 17.1.20 show examples for how to use a bus buffer and the timing charts. table 17.1.5 lists the memory chips that can be connected a without bus buffer. when using one of these memory chips, the user can connect it to the users microcomputer without a bus buffer because timing parameters t df and t dis(oe) listed below are guaranteed. (however, the read signal must go _ high within 10 ns after rising of e signal.) table 17.1.5 memory chips that can be connected without bus buffer t df /t dis(oe) (maximum) 15 ns (when guaranteeing by kit) (note) 8 ns 10 ns 6 ns 7 ns 8 ns conditions f(x in ) 20 mhz, at lowCspeed running f(x in ) 40 mhz, at highCspeed running f(x in ) 25 mhz, at lowCspeed running f(x in ) 25 mhz, at lowCspeed running f(x in ) 40 mhz, at highCspeed running f(x in ) 25 mhz, at lowCspeed running type description m5m27c256ak-85, -10, -12, -15 m5m27c512ak-10, -12, -15 m5m27c100k-12. -15 m5m27c101k-12, -15 m5m27c102k-12, -15 m5m27c201k, jk-10, -12, -15 m5m27c202k, jk-10, -12, -15 m5m27c256ap, fp, vp, rv-12, -15 m5m27c512ap, fp-15 m5m27c100p-15 m5m27c101p, fp, j, vp, rv-15 m5m27c102p, fp, j, vp, rv-15 m5m27c201p, fp, j, vp, rv-12, -15 m5m27c202p, fp, j, vp, rv-12, -15 m5m28f101p, fp, j, vp, rv-10, -12, -15 m5m28f102fp, j, vp, rv-10, -12, -15 m5m5256cp, fp, kp, vp, rv-55ll, -55xl, -70ll, -70xl, -85ll, -85xl, -10ll, -10xl m5m5278cp, fp, j-20, -20l m5m5278cp, fp, j-25, -25l m5m5278dp, j-12 m5m5278dp, fp, j-15, -15l m5m5278dp, fp, j-20, -20l note: when the user want specifications of the memory chips listed above, add a comment t df /t dis(oe) 15 ns product, microcomputer and kit.
applications 7751 group users manual 17C18 17.1 memory expansion fig. 17.1.13 example for using bus buffer (at lowCspeed runningC1) f245 byte a 8 /d 8 C a 15 /d 15 25 mhz data bus (odd) le dq oe ac573 dir ab le dq oe ac573 ale a 1 Ca 7 address bus m37751 dir ab e a 0 r/w bhe bc32 ac04 rd wo we ac32 x in x out circuit condition: 3 access in low-speed running f245 ] 2 ] 2 ] 3 a 16 /d 0 C a 23 /d 7 ] 1 cnv ss ] 4 oc oc data bus (even) ] 1: use the elements of which propagation delay time is within 20 ns. ] 2, ] 3 : use the elements of which sum of output disable time in ] 2 and propagation delay time in ] 3 is within 18 ns and the sum of output enable time in ] 2 and propagation delay time in ] 3 is 5 ns or more. ] 4: use the elements of which propagation delay time is within 12 ns.
applications 7751 group users manual 17C19 17.1 memory expansion fig. 17.1.14 timing chart for sample circuit using bus buffers (at lowCspeed running-1) a 8 /d 8 Ca 15 /d 15 a 16 /d 0 Ca 23 /d 7 e oc (f245), rd 5 (max.) 135 (min.) 18 (min.) bc32 (t phl ) bc32 (t plh ) d a f245 (t phz /t plz ) f245 (t pzh /t pzl ) a 8 /d 8 Ca 15 /d 15 a 16 /d 0 Ca 23 /d 7 e 135 (min.) bc32 (t plh ) d a d f245 (t phl /t plh ) (unit : ns) f245 (t phz /t plz ) oc (f245), wo, we 35 (max.) bc32 (t phl ) external memory data output a (f245) external memory data output b (f245) a a
applications 7751 group users manual 17C20 17.1 memory expansion fig. 17.1.15 example for using bus buffer (at low-speed running-2 : connecting with memory requiring long hold time for write) als245a byte e 16 mhz data bus (even) data bus (odd) le dq oe ac573 oc dir ab le dq oe ac573 ale a 1 Ca 7 address bus dir ab a 0 r/w bhe ac32 ac04 rd we wo 1d1q 1t 2d 2q 2t 1 ac74 ac32 ac04 x in x out als245a a 8 /d 8 C a 15 /d 15 m37751 a 16 /d 0 C a 23 /d 7 ] 1 ] 2 cnv ss ] 2 oc 1 this circuit ensures that the rising of the write signal occurs 1/2 1 clock earlier to extend the write hold time. circuit condition : 3 access in low-speed running ] 1: use the elements of which propagation delay time is within 42.5 ns. ] 2: use the elements of which output enable time is 5 ns or more and output disable time is within 40.5 ns.
applications 7751 group users manual 17C21 17.1 memory expansion fig. 17.1.16 timing chart for sample circuit using bus buffers (at low-speed running-2) a 8 /d 8 Ca 15 /d 15 a 16 /d 0 Ca 23 /d 7 rd 5 (max.) 225 (min.) 40.5 (min.) ac32 (t phl ) ac32 (t plh ) d a als245a (t phz /t plz ) e, oc (als245a) als245a (t pzh /t pzl ) (unit : ns) d a d ac32 5 2 (t plh ) als245a (t phz /t plz ) a 8 /d 8 Ca 15 /d 15 a 16 /d 0 Ca 23 /d 7 wo, we 2q(ac74) 1q (ac74) e, oc (als245a) ac04 (t plh )+ac74 (t plh ) 35 (max.) als245a (t phl /t plh ) 225 (min.) 1 1 external memory data output a (als245a) write hold time external memory data output b (als245a) a
applications 7751 group users manual 17C22 17.1 memory expansion fig. 17.1.17 example for using bus buffer (at high-speed running-1) f245 byte a 8 /d 8 C a 15 /d 15 40 mhz data bus (odd) le dq oe ac573 dir ab le dq oe ac573 ale a 1 Ca 7 address bus m37751 dir ab e a 0 r/w bhe bc32 ac04 rd wo we ac32 x in x out circuit condition: 5 access in high-speed running f245 ] 2 ] 2 ] 3 a 16 /d 0 C a 23 /d 7 ] 1 cnv ss ] 4 oc oc data bus (even) ] 1: use the elements of which propagation delay time is within 45 ns. ] 2, ] 3 : use the elements of which sum of output disable time in ] 2 and propagation delay time in ] 3 is within 15 ns, and the sum of output enable time in ] 2 and propagation delay time in ] 3 is 5 ns or more. ] 4: use the elements of which propagation delay time is within 40 ns.
applications 7751 group users manual 17C23 17.1 memory expansion a 8 /d 8 Ca 15 /d 15 a 16 /d 0 Ca 23 /d 7 e oc (f245), rd 5 (max.) 125 (min.) 15 (min.) bc32 (t phl ) bc32 (t plh ) d a a f245 (t phz /t plz ) f245 (t pzh /t pzl ) a 8 /d 8 Ca 15 /d 15 a 16 /d 0 Ca 23 /d 7 e 125 (min.) bc32 (t plh ) d a d f245 (t phl /t plh ) (unit : ns) f245 (t phz /t plz ) oc (f245), wo, we 35 (max.) external memory data output a (f245) external memory data output b (f245) fig. 17.1.18 timing chart for sample circuit using bus buffers (at high-speed running-1) a
applications 7751 group users manual 17C24 17.1 memory expansion fig. 17.1.19 example for using bus buffer (at high-speed running-2 : connecting with memory requiring long hold time for write) f245 byte e 40 mhz data bus (even) data bus (odd) le dq oe ac573 oc dir ab le dq oe ac573 ale a 1 Ca 7 address bus dir ab a 0 r/w bhe ac32 ac04 rd we wo 1d1q 1t 2d 2q 2t 1 ac74 ac32 ac04 x in x out f245 a 8 /d 8 C a 15 /d 15 m37751 a 16 /d 0 C a 23 /d 7 ] 1 ] 2 cnv ss ] 2 oc 1 this circuit ensures that the rising of the write signal occurs 1.5 1 clock earlier to extend the write hold time. circuit condition : 5 access in high-speed running ] 4 ] 3 ] 1: use the elements of which propagation delay time is within 45 ns. ] 2, ] 3 : use the elements of which sum of output disable time in ] 2 and propagation delay time in ] 3 is within 15 ns, and the sum of output enable time in ] 2 and propagation delay time in ] 3 is 5 ns or more. ] 4: use the elements of which propagation delay time is within 40 ns. bc32 ] 3
applications 7751 group users manual 17C25 17.1 memory expansion fig. 17.1.20 timing chart for sample circuit using bus buffers (at high-speed running-2) 5 (max.) 125 (min.) ac32 (t phl ) d a 15 (min.) ac32 (t plh ) a f245 (t phz /t plz ) f245 (t pzh /t pzl ) wo, we 2q (ac74) 1q (ac74) e 1 (unit : ns) d a d write hold time f245 (t phz /t plz ) 35 (max.) f245 (t phl /t plh ) oc (f245) bc32 (t plh ) bc32 (t phl ) 125 (min.) ac04 (t plh )+ac74 (t plh ) bc32 (t phl ) bc32 (t plh ) oc (f245) a 8 /d 8 Ca 15 /d 15 a 16 /d 0 Ca 23 /d 7 e rd external memory data output a (f245) external memory data output b (f245) 1 a 8 /d 8 Ca 15 /d 15 a 16 /d 0 Ca 23 /d 7 ac32 5 2(t plh )
applications 7751 group users manual 17C26 17.1 memory expansion 17.1.4 example of memory expansion (1) example of sram expansion (minimum model) figure 17.1.21 shows a memory expansion example (minimum model) using a 32-kbyte sram in the memory expansion mode at the low-speed running. figure 17.1.22 shows the timing chart for this example. figure 17.1.23 shows a memory expansion example (minimum model) using a 32-kbyte sram in the memory expansion mode at the high-speed running. figure 17.1.24 shows the timing chart for this example. fig. 17.1.21 example of sram expansion (minimum model at low-speed running) d 0 Cd 7 ac32 25 mhz x in x out m37751 byte r/w e open bhe a 0 Ca 13 oe s m5m5256cp-70ll a 14 cnv ss we 0880 16 sfr area internal ram area external ram area (m5m5256cp) memory map ] 2 0000 16 0080 16 ac32 ] 1 a 0 Ca 13 d 0 Cd 7 ] 1, ] 2: use the elements of which propagation delay time is within 18 ns. ffff 16 4000 16 circuit condition : 3 access in low-speed running internal rom area a 14
applications 7751 group users manual 17C27 17.1 memory expansion fig. 17.1.22 timing chart for sram expansion example (minimum model at low-speed running) d 0 Cd 7 external ram data output (a) (a) d s t a (ad) 135 (min.) 12 (min.) 5 (max.) 18 (min.) t a (oe) t su (p2d-e) 3 30 15 (max.) (kit guaranteed) e, oe ac32 (t plh ) ac32 (t phl ) t a (s) e, oe a 0 Ca 14 a d 0 Cd 7 s (a) (a) we d 135 (min.) t su (d) 3 30 ac32 (t phl ) ac32 (t plh ) 35 (max.) 18 (min.) ac32 (t plh ) ac32 (t phl ) a 0 Ca 14 a (unit : ns) t su (p0a/p1a/p2a-p1d/p2d) = 135 a
applications 7751 group users manual 17C28 17.1 memory expansion d 0 Cd 7 ac32 40 mhz x in x out m37751 byte r/w e open bhe a 0 Ca 13 oe s m5m5256cp-70ll a 14 cnv ss we 0880 16 sfr area internal ram area external ram area (m5m5256cp) memory map ] 2 0000 16 0080 16 ac32 ] 1 a 0 Ca 13 d 0 Cd 7 ] 1, ] 2: use the elements of which propagation delay time is within 15 ns. ffff 16 4000 16 circuit condition : 5 access in high-speed running internal rom area a 14 fig. 17.1.23 example of sram expansion (minimum model at high-speed running)
applications 7751 group users manual 17C29 17.1 memory expansion external ram data output (a) (a) d s t a (ad) 125 (min.) 40 (min.) 5 (max.) 15 (min.) t a (oe) t su (p2d-e) 3 30 15 (max.) (kit guaranteed) e, oe ac32 (t plh ) ac32 (t phl ) t a (s) e, oe a 0 Ca 14 a d 0 Cd 7 s (a) (a) w d 125 (min.) t su (d) 3 30 ac32 (t phl ) ac32 (t plh ) 35 (max.) 15 (min.) ac32 (t plh ) ac32 (t phl ) a 0 Ca 14 (unit : ns) t su (p0a/p1a/p2a-p1d/p2d) = 150 fig. 17.1.24 timing chart for sram expansion example (minimum model at high-speed running)
applications 7751 group users manual 17C30 17.1 memory expansion (2) example of rom expansion (maximum model) figure 17.1.25 shows a memory expansion example (maximum model) using a 1-mbits rom in the microprocessor mode. figure 17.1.26 shows the timing chart for this example. figure 17.1.27 shows a memory expansion example (maximum model) using a 1-mbits rom in the microprocessor mode. figure 17.1.28 shows the timing chart for this example. fig. 17.1.25 example of rom expansion (maximum model at low-speed running) a 0 C a 15 m5m27c102k-12 oe a 1 Ca 7 ac04 25 mhz x in x out m37751 byte data bus a 1 Ca 16 address bus a 16 /d 0 ale d 1 Cd 7 e r/w a 8 /d 8 C a 15 /d 15 ac573 ce d 0 Cd 15 d 0 C d 15 a 8 Ca 15 0000 16 0080 16 sfr ar ea internal ram area external rom area (m5m27c102k) memory map q le d cnv ss [ 2 [ 1 ac573 q le d a 16 1ffff 16 0880 16 circuit condition : 3 access in low-speed running ] 1: use the elements of which propagation delay time is within 15 ns. ] 2: use the elements of which propagation delay time is within 23 ns.
applications 7751 group users manual 17C31 17.1 memory expansion fig. 17.1.26 timing chart for rom expansion example (maximum model at low-speed running) a 8 /d 8 Ca 15 /d 15 a 16 /d 0 a 135 (min.) 12 (min.) t a (ad) +ac573 (t phl /t plh ) ce t a (oe) r/w 20 (min.) t a (ce) ac04 (t phl ) 18 (min.) a 5 (max.) d ( kit guaranteed ) t su (p1d/p2d-e) 3 30 18 (max.) e, oe ac04 (t plh ) 15 (max.) (unit : ns) external rom data output t su (p0a/p1a/p2a-p1d/p2d) = 135
applications 7751 group users manual 17C32 17.1 memory expansion fig. 17.1.27 example of rom expansion (maximum model at high-speed running) fig. 17.1.28 timing chart for rom expansion example (maximum model at high-speed running) a 0 C a 15 m5m27c102k-12 oe a 1 Ca 7 ac04 40 mhz x in x out m37751 byte data bus a 1 Ca 16 address bus a 16 /d 0 ale d 1 Cd 7 e r/w a 8 /d 8 C a 15 /d 15 ac573 ce d 0 Cd 15 d 0 C d 15 a 8 Ca 15 0000 16 0080 16 sfr area internal ram area external rom area (m5m27c102k) memory map q le d cnv ss [ 2 [ 1 ac573 q le d a 16 1ffff 16 0880 16 circuit condition : 5 access in high-speed running ] 1: use the elements of which propagation delay time is within 30 ns. ] 2: use the elements of which propagation delay time is within 35 ns. a 8 /d 8 Ca 15 /d 15 a 16 /d 0 a 125 (min.) 40 (min.) t a (ad) +ac573 (t phl /t plh ) ce t a (oe) r/w 45 (min.) t a (ce) ac04 (t phl ) 15 (min.) a 5 (max.) d ( kit guaranteed ) t su (p1d/p2d-e) 3 30 15 (max.) e, oe ac04 (t plh ) 15 (max.) (unit : ns) external rom data output t su (p0a/p1a/p2a-p1d/p2d) = 150
applications 7751 group users manual 17C33 17.1 memory expansion fig. 17.1.29 example of rom and sram expansion (maximum model at low-speed running) (3) example of rom and sram expansion (maximum model) figure 17.1.29 shows a memory expansion example (maximum model) using two 32-kbytes rom and two 32-kbytes sram in the microprocessor mode at the low-speed running. figure 17.1.30 shows the timing chart for this example. figure 17.1.31 shows a memory expansion example (maximum model) using two 32-kbytes rom and two 32-kbytes sram in the microprocessor mode at the high-speed running. figure 17.1.32 shows the timing chart for this example. 0000 16 0080 16 external rom area (m5m27c256ak 5 2) sfr area internal ram area external ram area (m5m5256cp 5 2) memory map ac32 ac04 21 mhz x in x out m37751 byte a16 a8 C a15 data bus (odd) ac573 dq le ac32 ac04 rd d0 C d7 d8 C d15 address bus wo a 0 Ca 14 d 0 Cd 7 m5m27c256ak-15 a1 C a15 d 0 Cd 7 oe a 0 Ca 14 ce a1 C a15 s s a 0 Ca 14 a 0 Ca 14 dq 1 Cdq 8 dq 1 Cdq 8 oe w oe w a1 C a15 a1 C a15 d0 C d7 m5m5256cp-70ll oe d8 C d15 ce we a 1 Ca 7 a 8 /d 8 C a 15 /d 15 ale a 16 /d 0 d 1 Cd 7 r/w e a 0 bhe cnv ss [ 2 [ 1 ] 3 ac573 dq le [ 2 1ffff 16 10000 16 0880 16 data bus (even) circuit condition : 3 access in low-speed running ] 1: use the elements of which propagation delay time is within 80 ns. ] 2: use the elements of which propagation delay time is within 23 ns. ] 3: use the elements of which propagation delay time is within 10.6 ns.
applications 7751 group users manual 17C34 17.1 memory expansion fig. 17.1.30 timing chart for rom and sram expansion example (maximum model at low-speed running) a 1 Ca 7 a e a 8 / d 8 Ca 15 / d 15 a 16 / d 0 , d 1 Cd 7 s a d 165.4 (min.) 35 (max.) 19.6 (min.) ac32 (t phl ) t su (d) 3 30 (unit: ns) we, wo ac573 (t phl )+ac04 (t phl ) ac32 (t plh ) a 8 / d 8 Ca 15 / d 15 a 16 / d 0 external memory data output a d e 165.4 (min.) 19.6 (min.) 5 (max.) 25.6 (min.) (kit guaranteed) t a (ad), t a (ce) t su (p1d/p2d-e) 3 30 t a (s) oe ac32 (t plh ) a 1 Ca 7 a ce, s t a (oe) ac04 (t phl ) ac573 (t phl ) ce s ac32 (t phl ) 15 (max.) 25.6 (min.) t su(p0a/p1a/p2aCp1d/p2d) = 173 a a a a
applications 7751 group users manual 17C35 17.1 memory expansion fig. 17.1.31 example of rom and sram expansion (maximum model at high-speed running) 0000 16 0080 16 external rom area (m5m27c256ak 5 2) sfr area internal ram area external ram area (m5m5256cp 5 2) memory map bc32 ac04 31 mhz x in x out m37751 byte a16 a8 C a15 data bus (odd) ac573 dq le ac32 ac04 rd d0 C d7 d8 C d15 address bus wo a 0 Ca 14 d 0 Cd 7 m5m27c256ak-12 a1 C a15 d 0 Cd 7 oe a 0 Ca 14 ce a1 C a15 s s a 0 Ca 14 a 0 Ca 14 dq 1 Cdq 8 dq 1 Cdq 8 oe w oe w a1 C a15 a1 C a15 d0 C d7 m5m5256cp-70ll oe d8 C d15 ce we a 1 Ca 7 a 8 /d 8 C a 15 /d 15 ale a 16 /d 0 d 1 Cd 7 r/w e a 0 bhe cnv ss ] 2 ] 1 ] 3 ac573 dq le ] 2 1ffff 16 10000 16 0880 16 data bus (even) circuit condition : 4 access in high-speed running ] 1: use the elements of which propagation delay time is within 50 ns. ] 2: use the elements of which propagation delay time is within 30 ns. ] 3: use the elements of which propagation delay time is within 7.2 ns. ] 4: use the elements of which propagation delay time is within 22.2 ns. ] 4
applications 7751 group users manual 17C36 17.1 memory expansion fig. 17.1.32 timing chart for rom and sram expansion example (maximum model at high-speed running) a 104 (min.) 61.7 (min.) 5 (max.) t a (ad), t a (ce) a t a (oe) ac573 (t phl ) ce s a a d 104 (min.) 61.7 (min.) ac32 (t phl ) t su (d) 3 30 ac04 (t phl ) t su (p0a/p1a/p2a-p1d/p2d) = 150 t su (p1d/p2d-e) 3 30 bc32 (t phl ) a 22.2 (min.) bc32 (t plh ) a a a ac32 (t plh ) t a (s) d ac573 (t phl )+ac04 (t phl ) 35 (max.) 15 (max.) 22.2 (min.) a 8 / d 8 Ca 15 / d 15 a 16 / d 0 external memory data output e oe a 1 Ca 7 ce, s a 1 Ca 7 e a 8 / d 8 Ca 15 / d 15 a 16 / d 0 , d 1 Cd 7 s we, wo (unit: ns) (kit guaranteed)
applications 7751 group users manual 17C37 17.1 memory expansion 17.1.5 example of i/o expansion (1) example of port expansion circuit using m66010fp figure 17.1.33 shows an example of a port expansion circuit using the m66010fp. although figure 17.1.33 is an expansion example in the high-speed running, when using 1.923 mhz or less frequency for serial i/o transfer clock, the same expansion is possible regardless of the bus cycle. about serial i/o control in this expansion example is described below. in this example, 8-bit data transmission/reception is performed 3 times by using uart0 and 24-bit port expansion is realized. setting of uart0 is described below: l clock synchronous serial i/o mode: transmission/reception enable state l internal clock is selected. transfer clock frequency is 1.66 mhz. l lsb first the control process is described below: output l level from port p4 5 . (expansion i/o ports of m66010fp become floating state by this signal. ) output h level from port p4 5 . a output l level from port p4 4 . ? transmit/receive 24-bit data by using uart0. ? output h level from port p4 4 . figure 17.1.34 shows serial transfer timing between m37751 and m66010fp.
applications 7751 group users manual 17C38 17.1 memory expansion fig. 17.1.33 example of port expansion circuit using m66010fp circuit condition: ?uart0 used in clock synchronous serial i/o mode ?internal clock selected ?frequency of transfer clock = = 1.66 mhz 40 mhz txd 0 rxd 0 clk 0 p4 4 p4 5 rts 0 m37751 x in x out di do clk cs s v cc gnd cnv ss byte m66010fp d1 d2 d3 d4 d5 d6 d7 d8 d9 d10 d11 d12 d13 d14 d15 d16 d17 d18 d19 d20 d21 d22 d23 d24 a 0 Ca 7 a 8 /d 8 C a 15 /d 15 a 16 /d 0 C a 23 /d 7 ale e 1 r/w bhe open expanded i/o port f 4 2 (2 + 1)
applications 7751 group users manual 17C39 17.1 memory expansion fig. 17.1.34 serial transfer timing between m37751 and m66010fp do1 do2 do3 do4 do5 do6 do7 do8 do20 do21 do22 do23 do24 di1 di2 di3 di4 di5 di6 di7 di8 di20 di21 di22 di23 di24 di1 di2 di24 s cs clk di do expanded i/o port do24 do2 do1 d1 d2 d24 p4 5 p4 4 clk 0 t x d 0 r x d 0 expanded i/o port expanded i/o port terminating floating of expanded i/o ports inputting data of expanded i/o ports to shift register 1 inputting serial data to shift register 2 serial outputting data of shift register 1 ] expanded i/o ports are n- channel open- drain out put type. : m37751s pin name (the others are m66010fps pin name and operation. outputting data of shift register 2 to expanded i/o ports to
applications 7751 group users manual 17C40 17.1 memory expansion memorandum
chapter 18 prom version 18.1 eprom mode 18.2 usage precaution
prom version 7751 group users manual 18C2 in the prom version, programming/reading to and from the built-in prom can be performed by using a general-purpose prom programmer and a programming adapter. the prom version has the following two types : l one time prom version programming to the prom can be performed once. this version is suitable for a small quantity of and various productions. l eprom version programming to the prom can be performed repeatedly because a program can be erased by exposing the erase window on the top of the package to an ultraviolet light source. this version can be used only for program development, evaluation only. the prom version have the same functions as the mask rom version except that the former have a built- in prom. table 18.1.1 lists the product expansion of the prom version. table 18.1.1 product expansion of prom version prom size one time prom 49152 bytes eprom 49152 bytes type name m37751e6c-xxxfp (m37751e6cfp) m37751e6cfs ram size 2048 bytes
prom version 7751 group users manual 18C3 18.1 eprom mode the prom version can select the normal operating mode which performs the same operation as that of the mask rom version, or the eprom mode which enables to program/read to/from the built-in prom. ______ when l level is input to the reset pin, the prom version enters the eprom mode. 18.1.1 pin description table 18.1.2 lists the pin description in the eprom mode. table 18.1.2 pin description in eprom mode 18.1 eprom mode input/output CC input input input output output CC input input input i/o input input input input input input name power source input v pp input reset input clock input clock output enable output analog power source input reference voltage input address input (a 0 Ca 7 ) address input (a 8 Ca 15 ) data input/output (d 0 Cd 7 ) input port p3 input port p4 control input input port p5 input port p6 input port p7 input port p8 pin v cc , v ss cnv ss byte ______ reset x in x out _ e av cc , av ss v ref p0 0 Cp0 7 p1 0 Cp1 7 p2 0 Cp2 7 p3 0 Cp3 3 p4 0 Cp4 7 p5 0 p5 1 p5 2 p5 3 Cp5 6 p5 7 p6 0 Cp6 7 p7 0 Cp7 7 p8 0 Cp8 7 functions apply 5 v 10% to v cc pin, and 0 v to v ss pin. apply v pp level when programming or verifying. connect to v ss pin. connect a ceramic resonator or a quartz-crystal oscillator between x in and x out pins. when an external generated clock is input, the clock must be input to x in pin, and x out pin must be left open. open. connect av cc pin to v cc pin and av ss pin to v ss pin. connect to v ss pin. input pins for a 0 Ca 7 of addresses. input pins for a 8 Ca 15 of addresses. i/o pins for data d 0 Cd 7 . connect to v ss pin. connect to v ss pin. _____ p5 0 functions as pgm input pin. ___ p5 1 functions as oe input pin. ___ p5 2 functions as ce input pin. connect to v cc pin. connect to v ss pin. connect to v ss pin.
prom version 7751 group users manual 18C4 18.1 eprom mode 18.1.2 programming/reading eprom mode can perform programming/reading to and from the built-in prom with the same manner as m5m27c101k. however, there is no device identification code. accordingly, programming conditions must be set carefully. perform the programming to addresses 14000 16 to 1ffff 16 . table 18.1.3 lists the pin correspondence with m5m27c101k. figure 18.1.1 shows the pin connections in eprom mode. table 18.1.4 lists the built-in prom states in eprom mode. table 18.1.3 pin correspondence with m5m27c101k m5m27c101k vcc v pp vss a 0 Ca 15 d 0 Cd 7 ce oe pgm vcc v pp input vss address input data i/o __ ce input __ oe input ____ pgm input vcc cnvss, byte vss p0, p1 p2 p5 2 p5 1 p5 0 m37751e6c-xxxfp (m37751e6cfp) m37751e6cfs
prom version 7751 group users manual 18C5 18.1 eprom mode fig. 18.1.1 pin connections in eprom mode 66 p8 2 /rxd 0 67 p8 1 /clk 0 1 p6 6 /tb1 in 2 p6 5 /tb0 in 3 p6 4 /int 2 4 p6 3 /int 1 5 p6 2 /int 0 6 p6 1 /ta4 in 7 p6 0 /ta4 out 8 p4 1 /rdy 64 p8 4 /cts 1 /rts 1 63 p8 5 /clk 1 62 p8 6 /rxd 1 61 p8 7 /txd 1 60 p0 0 /a 0 59 p0 1 /a 1 58 p0 2 /a 2 57 p0 3 /a 3 9 10 p5 7 /ta3 in 11 p5 6 /ta3 out 12 p5 5 /ta2 in 13 p5 4 /ta2 out 14 p5 3 /ta1 in 15 p5 2 /ta1 out 16 p5 1 /ta0 in 17 p5 0 /ta0 out 18 p4 7 19 p4 6 20 p4 5 21 p4 4 22 p4 3 23 p4 2 / 1 24 56 p0 4 /a 4 55 p0 5 /a 5 54 p0 6 /a 6 53 p0 7 /a 7 52 p1 0 /a 8 /d 8 51 p1 1 /a 9 /d 9 50 p1 2 /a 10 /d 10 49 p1 3 /a 11 /d 11 48 p1 4 /a 12 /d 12 47 p1 5 /a 13 /d 13 46 p1 6 /a 14 /d 14 45 p1 7 /a 15 /d 15 44 p2 0 /a 16 /d 0 43 p2 1 /a 17 /d 1 42 p2 2 /a 18 /d 2 41 p2 3 /a 19 /d 3 80 p7 1 /an 1 79 p7 2 /an 2 78 p7 3 /an 3 77 p7 4 /an 4 76 p7 5 /an 5 75 p7 6 /an 6 74 p7 7 /an 7 /ad trg 73 v ss 72 av ss 71 v ref 70 av cc 69 v cc 68 p8 0 /cts 0 /rts 0 65 p8 3 /txd 0 39 p2 5 /a 21 /d 5 38 p2 6 /a 22 /d 6 25 p4 0 /hold 26 byte 27 cnv ss 28 reset 29 x in 30 x out 31 v ss 33 p3 3 /hlda 34 p3 2 /ale 35 p3 1 /bhe 36 p3 0 /r/w 37 p2 7 /a 23 /d 7 40 p2 4 /a 20 /d 4 m37751e6c-xxxfp outline : 80p6n-a ] : connect an oscillating circuit. a 7 a 6 a 5 a 4 a 3 a 2 a 1 a 0 a 8 a 9 a 10 a 11 a 12 a 13 a 14 d 0 d 1 d 2 d 3 oe ce v pp d 4 d 5 d 6 d 7 v ss ] a 15 pgm v cc e p7 0 /an 0 p6 7 /tb2 in eprom pins : 32
prom version 7751 group users manual 18C6 18.1 eprom mode table 18.1.4 built-in prom state in eprom mode pin name data i/o output floating floating input output floating v il v il v ih v il v il v ih v il v ih 5 v ih v il v ih 5 5 5 v il v ih v ih 5 v 5 v 5 v 12.5 v 12.5 v 12.5 v vcc v pp pgm ce 5 v 5 v 5 v 6 v 6 v 6 v oe mode read-out output disable program program verify program disable 5 : it may be v il or v ih . (1) read ___ ___ when ce and oe pins are set to l level and an address is input to address input pins, the data of the specified address, input address, is output externally from data i/o pins. ___ ___ when ce and oe pins are set to h level, data i/o pins enter the floating state. (2) program (write) ___ ___ when ce pin is set to l level and oe pin is set to h level and v pp level is applied to v pp pin, programming to the built-in prom becomes possible. input an address to address input pins and supply data to be programmed to data i/o pins in 8-bit ____ parallel. in this condition, when pgm pin is set to l level, the data is programmed at the specified address, input address, into the built-in prom. (3) erase (possible only in eprom version) the contents of the built-in prom is erased by exposing the glass window on top of the package to an ultraviolet light which has a wave length of 2537 angstrom. the light must be 15 j/cm 2 or more.
prom version 7751 group users manual 18C7 18.1.3 programming algorithm of built-in prom set vcc = 6 v, v pp = 12.5 v, and address to 14000 16 . after applying a programming pulse of 0.2 ms, check whether data can be read or not. a if the data cannot be read, apply a programming pulse of 0.2 ms again. ? repeat the procedure, which consists of applying a programming pulse of 0.2 ms and read check, until the data can be read. additionally, record the number of applied pulses ( c ) before the data has been read. ? apply c pulse (0.2 5 c ms) (described in ? ) as additional programming pulses. ? when this procedure ( to ? ) is completed, increment the address and repeat the above procedure until the last address is reached. ? after programming to the last address, read data when vcc = v pp = 5 v (or vcc = v pp = 5.5 v). figure 18.1.2 shows the programming algorithm flowchart. 18.1 eprom mode
prom version 7751 group users manual 18C8 fig. 18.1.2 programming algorithm flow chart 18.1 eprom mode verify all byte start addr = first location c = 0 v cc = v pp = *5.0 v device failed device passed v cc = 6.0 v v pp = 12.5 v c = c +1 c = 25 ? increment addr verify byte device failed last addr ? fail yes no pass pass yes fail pass no fail *4.5 v v cc = v pp 5.5 v verify byte program one pulse of 0.2 ms program pulse of 0.2 c ms duration
prom version 7751 group users manual 18C9 ac electrical characteristics (ta = 255 c, vcc = 60.25 v, v pp = 12.50.3 v, unless otherwise noted) 18.1.4 electrical characteristics of programming algorithm max. 130 0.21 5.25 150 typ. 0.2 min. limits unit parameter s s s s s ns s s ms ms s ns address setup time oe setup time data setup time address hold time data hold time ___ output floating delay time after oe vcc setup time v pp setup time ____ pgm pulse width ____ additional pgm pulse width ___ ce setup time ___ data delay time after oe t as t oes t ds t ah t dh t dfp t vcs t vps t pw t opw t ces t oe symbol 2 2 2 0 2 0 2 2 0.19 0.19 2 18.1 eprom mode t vcs t vps t ds t dh t dfp t as t opw t pw t ah verify program data set data output valid v ih v il v ih /v oh v il /v ol v pp v cc v cc +1 v cc v ih v il v ih v il address data ce oe v pp v cc t oes t oe v ih v il pgm t ces programming timing diagram switching characteristics measuring conditions l input voltage : v il = 0.45 v, v ih = 2.4 v l input signal rise/fall time (10 % ?90 %) : 20 ns l reference voltage in timing measurement : input/output ??= 0.8 v, ??= 2 v
7751 group users manual prom version 18C10 18.2 usage precaution 18.2 usage precaution 18.2.1 precautions on all prom versions l when programming to the built-in prom, high voltage is required. accordingly, be careful not to apply excessive voltage to the microcomputer. furthermore, be especially careful during power-on. l noise gets in easily because the built-in prom is wired directly from cnv ss (v pp ) pin. to prevent noise, the wiring of cnv ss (v pp ) pin is performed below. figure 18.2.1 shows the wiring of cnv ss (v pp ) pin. connect cnv ss (v pp ) pin to the microcomputers v ss pin in the shortest possible distance. if the wiring cannot be shortened, insert a resistor of about 5 kohms as close to cnv ss (v pp ) pin as possible. by way of this resistor, connect cnv ss (v pp ) pin to v ss pin. connect cnv ss (v pp ) pin to the microcomputers v cc pin in the shortest possible distance. in microprocessor mode cnv ss (v pp ) v cc m37751 shortest possible distance approx. 5 kohms cnv ss (v pp ) v ss m37751 ] the above processing is unnecessary for the byte (v pp ) pin. in single-chip and memory expansion modes shortest possible distance figure 18.2.1 wiring of cnv ss (v pp ) pin
prom version 7751 group users manual 18C11 18.2 usage precaution 18.2.2 precautions on one time prom version one time prom version shipped in a blank (m37751e6cfp), of which built-in prom is programmed by users, is also provided. for the microcomputer, a programming test and screening are not performed in the assembly process and the following processes. to improve their reliability after programming, we recommend to program and test as the flow shown in figure 18.2.2 before use. screening (leave at 150 ? for 40 hours) (note) verify test with prom programmer function check in target device note: never expose to 150 ? exceeding 100 hours. programming with prom programmer fig. 18.2.2 programming and test flow for one time prom version 18.2.3 precautions on eprom version l cover the transparent glass window with a shield or others during the read mode because exposing to sun light or fluorescent lamp can cause erasing the programmed data. be careful that the shield does not touch the eprom lead pins. a shield to cover the transparent window is available from mitsubishi electric corporation. l clean the transparent glass before erasing. there is a possibility that fingers fat and paste disturb the passage of ultraviolet rays and affect badly the erasure capability. l the eprom version is a tool only for program development, evaluation only, and do not use it for the mass product run.
7751 group users manual prom version 18C12 18.2 usage precaution memorandum
chapter 19 flash memory version 19.1 parallel input/output mode 19.2 serial input/output mode
flash memory version 7751 group users manual 19C2 in the flash memory version m37751f6cfp, to perform program, read, and erase operations for the built- in flash memory is possible. the m37751f6cfp has the same function as the mask rom version except for the builtCin flash memory (note) . the m37751f6cfp can select the microcomputer mode, which is performed the same operation as the mask rom version, or the flash memory mode, which enables to access to the builtCin flash memory. when ______ inputting l level to the reset pin, the m37751f6cfp enters the flash memory mode. in the flash memory mode, there are two modes: the parallel input/output mode and the serial input/output mode. note: ports p4 5 and p4 6 peripheral circuits are different from those of mask rom version. l microcomputer mode l flash memory mode fig. 19.1.1 operation mode for flash memory version fig. 19.1.2 ports p4 5 and p4 6 peripheral circuit (flash memory version) p4 5 , p4 6 data bus direction register port latch serial input/output mode parallel input/output mode read/write mode readConly mode
flash memory version 7751 group users manual 19C3 19.1 parallel input/output mode the built-in flash memory can be accessed by using a general purpose rom programmer in the parallel i/o mode. in this mode, the readConly mode or the read/write mode (software command control mode) can be selected as the builtCin flash memory mode with the voltage applied to the v pp (cnv ss ) pin. 19.1 parallel input/output mode
flash memory version 7751 group users manual 19C4 19.1.1 pin description table 19.1.1 lists the pin description in the parallel i/o mode. table 19.1.1 pin description in parallel i/o mode input/output input input input input output output input input input input/output input input input input input input name power supply v pp input external data bus width select input reset input clock input clock output enable output analog supply input reference voltage input address input a 0 to a 7 address input a 8 to a 15 data input/output d 0 to d 7 input port p3 input port p4 control signal input input port p5 address input a 16 input port p5 input port p6 input port p7 input port p8 functions supply 5 v 10 % to vcc pin and 0 v to vss pin. [read-only mode] supply vcc to vcc +1.0 v. [read/write mode] supply 12 v 5 %. connect to vss pin. connect to vss pin. connect a ceramic resonator or quartz-crystal oscillator between x in and x out pins. when using an external clock, the clock source must be input to x in pin and x out pin must be left open. left open. connect to vcc pin. connect to vss pin. connect to vss pin. these are address a 0 Ca 7 input pins. these are address a 8 Ca 15 input pins. these are data d 0 Cd 7 input/output pins. connect to vss pin. connect to vss pin. left open. connect to vss pin. ___ this is we signal input pin. ___ this is oe signal input pin. ___ this is ce signal input pin. connect to vcc pin. this is address a 16 input pin. connect to vss pin. connect to vss pin. 19.1 parallel input/output mode pin vcc, vss cnvss byte ______ reset x in x out _ e avcc avss v ref p0 0 Cp0 7 p1 0 Cp1 7 p2 0 Cp2 7 p3 0 Cp3 3 p4 0 , p4 1 p4 2 p4 3 to p4 7 p5 0 p5 1 p5 2 p5 3 p5 4 p5 5 to p5 7 p6 0 to p6 7 p7 0 to p7 7 p8 0 to p8 7
flash memory version 7751 group users manual 19C5 19.1.2 access to builtCin flash memory in the parallel i/o mode, the builtCin flash memory can be accessed with the same operation as cmos flash memory m5m28f101. however, because the builtCin flash memory has a capacity of 48 kbytes, use addresses 04000 16 to 0ffff 16 for programming and write ff 16 to addresses 00000 16 to 03fff 16 and 10000 16 to 1ffff 16 . the m37751f6cfp does not contain a facility to read out a device identification code by applying a high voltage to a 9 (p1 1 ) pin. do not erratically set program conditions etc.. table 19.1.2 lists the pin correspondence of the m37751f6cfp and the m5m28f101. figure 19.1.3 shows the pin connection in the parallel i/o mode. 19.1 parallel input/output mode vcc v pp input vss address input data i/o ___ ce signal input ___ oe signal input ___ we signal input m37751f6cfp vcc cnvss vss p0, p1, p5 4 p2 p5 2 p5 1 p5 0 m5m28f101 vcc v pp vss a 0 to a 16 d 0 to d 7 ___ ce ___ oe ___ we table 19.1.2 pin correspondence of m37751f6cfp and m5m28f101 (parallel i/o mode)
flash memory version 7751 group users manual 19C6 fig. 19.1.3 pin connection in parallel i/o mode 19.1 parallel input/output mode ] : connect to oscillation circuit. a 16 v ss ] ce oe we v cc 66 p8 2 /rxd 0 67 p8 1 /clk 0 1 p6 6 /tb1 in 2 p6 5 /tb0 in 3 p6 4 /int 2 4 p6 3 /int 1 5 p6 2 /int 0 6 p6 1 /ta4 in 7 p6 0 /ta4 out 8 p4 1 /rdy 64 p8 4 /cts 1 /rts 1 63 p8 5 /clk 1 62 p8 6 /rxd 1 61 p8 7 /txd 1 60 p0 0 /a 0 59 p0 1 /a 1 58 p0 2 /a 2 57 p0 3 /a 3 9 10 p5 7 /ta3 in 11 p5 6 /ta3 out 12 p5 5 /ta2 in 13 p5 4 /ta2 out 14 p5 3 /ta1 in 15 p5 2 /ta1 out 16 p5 1 /ta0 in 17 p5 0 /ta0 out 18 p4 7 19 p4 6 20 p4 5 21 p4 4 22 p4 3 23 p4 2 / 1 24 56 p0 4 /a 4 55 p0 5 /a 5 54 p0 6 /a 6 53 p0 7 /a 7 52 p1 0 /a 8 /d 8 51 p1 1 /a 9 /d 9 50 p1 2 /a 10 /d 10 49 p1 3 /a 11 /d 11 48 p1 4 /a 12 /d 12 47 p1 5 /a 13 /d 13 46 p1 6 /a 14 /d 14 45 p1 7 /a 15 /d 15 44 p2 0 /a 16 /d 0 43 p2 1 /a 17 /d 1 42 p2 2 /a 18 /d 2 41 p2 3 /a 19 /d 3 80 p7 1 /an 1 79 p7 2 /an 2 78 p7 3 /an 3 77 p7 4 /an 4 76 p7 5 /an 5 75 p7 6 /an 6 74 p7 7 /an 7 /ad trg 73 v ss 72 av ss 71 v ref 70 av cc 69 v cc 68 p8 0 /cts 0 /rts 0 65 p8 3 /txd 0 39 p2 5 /a 21 /d 5 38 p2 6 /a 22 /d 6 25 p4 0 /hold 26 byte 27 cnv ss 28 reset 29 x in 30 x out 31 32 v ss 33 p3 3 /hlda 34 p3 2 /ale 35 p3 1 /bhe 36 p3 0 /r/w 37 p2 7 /a 23 /d 7 40 p2 4 /a 20 /d 4 m37751f6cfp e p7 0 /an 0 p6 7 /tb2 in v pp outline : 80p6n-a a 0 d 3 a 1 a 2 a 14 a 15 d 0 d 1 d 2 a 3 a 4 a 5 a 6 a 7 a 8 a 9 a 10 a 11 a 12 a 13 d 7 d 4 d 5 d 6
flash memory version 7751 group users manual 19C7 19.1 parallel input/output mode 19.1.3 readConly mode when connecting shown in figure 19.1.3 and v pp l level is applied to the v pp pin, the builtCin flash memory operates at the readConly mode. in the readConly mode, the builtCin flash memory becomes read, output disable, or standby state depending on the control signals. in this mode, the contents of the builtCin flash memory can be read. table 19.1.3 lists the states of the builtCin flash memory. table 19.1.3 states of control signals and builtCin flash memory in readConly mode ___ ce v il v il v ih ___ oe ___ we v pp v pp l v pp l v pp l pin state data i/o read output disable standby v il v ih 5 v ih v ih 5 output floating floating note: 5 can be v il or v ih . (1) read when inputting the address of a memory location to be read and the control signals at the timing shown in figure 19.1.4, data of the specified address (input address) is output to an external. read address a 0 a 16 ce oe we d 0 d 7 t rc t wrr t a (ce) t a (oe) t olz t clz t a (ad) t df t oh data floating read data output floating fig. 19.1.4 read timing
flash memory version 7751 group users manual 19C8 19.1 parallel input/output mode (2) output disable the microcomputer enters the read disable state. (3) standby the microcomputer enters the powerCsaving state and the supply current decreases.
flash memory version 7751 group users manual 19C9 19.1 parallel input/output mode 19.1.4 read/write (software command control) mode when connecting shown in figure 19.1.3 and v pp h level is applied to the v pp pin, the builtCin flash memory operates at the read/write mode. in the read/write mode, the builtCin flash memory becomes read, output disable, standby or program state depending on the control signals. in this mode, program, read, and erase operations can be performed to the builtCin flash memory. table 19.1.4 lists the states of the builtCin flash memory. table 19.1.4 states of control signals and builtCin flash memory in read/write mode ___ ce ___ oe ___ we v pp v pp h v pp h v pp h v pp h pin state data i/o read output disable standby program v il v ih 5 v ih v ih v ih 5 v il output floating floating input v il v il v ih v il notes 1: 5 can be v il or v ih . 2: refer to (5) software command for read and write states. (1) read when executing the read command or program verify command etc., the read mode is used. (refer to (5) software command. ) (2) output disable the microcomputer enters the read disable state. (3) standby the microcomputer enters the powerCsaving state and the supply current decreases. (4) program when inputting the command code or program data etc., the program mode is used. (refer to (5) software command. )
flash memory version 7751 group users manual 19C10 19.1 parallel input/output mode (5) software command in the read/write mode, the builtCin flash memory is accessed by input (execution) of the software command. table 19.1.5 lists the software command. the software command is executed by data input/output in the first and second cycles. the command code is input to select the operation of the builtCin flash memory in the first cycle. the data etc. are input/output in the second cycle. the following explains each software command. table 19.1.5 software command and input/output information read program program verify erase erase verify reset device identification first cycle software command address input 5 5 5 5 verify address 5 5 second cycle data i/o read data output program data input verify data output 20 16 (command code) input verify data output ff 16 (command code) input ddi output address input read address program address 5 5 5 5 adi data (command code) input 00 16 40 15 c0 16 20 16 a0 16 ff 16 90 16 note: 5 can be v il or v ih . adi (device identification address) : manufactures code 00000 16 ; device code 00001 16 ddi (device identification data) : manufactures code 1c 16 ; device code d0 16
flash memory version 7751 group users manual 19C11 19.1 parallel input/output mode read address t rc a 0 ? 16 ce oe we d 0 ? 7 t olz t clz t a (ad) t a (oe) 00 16 t df t oh floating read data output t a (ce) t wc t rrw t ch t wrr t cs t ds data t vsc second cycle first cycle v pp h v pp l v pp t wp t dh floating floating l read command figure 19.1.5 shows the read command execution timing. ___ the command code is latched into the internal command latch at the rising edge of the we signal by inputting the control signals and the command code 00 16 in the first cycle. the data of the specified address (input address) is output to an external by inputting the address and control signals in the second cycle. the read command code which is latched into the command latch is retained until any other command code is latched into the command latch. accordingly, when the second cycle input over again after the read command code is input in the first cycle, the read command is executed over again. the read command code is latched into the command latch after powerCon. fig. 19.1.5 read command execution timing note: when executing any command other than the read command, input the command code (input from the first cycle) each time the execution.
flash memory version 7751 group users manual 19C12 19.1 parallel input/output mode l program command figure 19.1.6 shows the program command and the program verify command execution timing. ___ the command code is latched into the internal command latch at the rising edge of the we signal by inputting the control signals and the command code 40 16 in the first cycle. ___ the address is latched into the internal at the falling edge of the we signal and the data is latched ___ at the rising edge of the we signal by inputting the address, data, and control signals in the second cycle. ___ the program is started at the rising edge of the we signal in the second cycle and the input data is programmed to the specified address (input address) within 10 s as measured by its internal timer. programming is performed by the byte unit. note: be sure to execute a program verify command after executing the program command. if this verification fails, execute repeatedly the program command and the program verify command until the verification passes. (refer to 19.1.6 program/erase algorithm flow chart. ) l program verify command this command is executed to verify the program data after executing the program command. ___ the command code is latched into the internal command latch at the rising edge of the we signal by inputting the control signals and the command code c0 16 in the first cycle. the data of the address where the program command is executed is output to an external by inputting the control signals in the second cycle. since the address is internally latched when the program command is executed, there is no need to input it when the program verify command is executed.
flash memory version 7751 group users manual 19C13 19.1 parallel input/output mode fig. 19.1.6 program command and program verify command execution timing floating t rc t wc a 0 Ca 16 ce oe we d 0 Cd 7 t wph t cs 40 16 t df t oh floating verify data output t rrw t ch t cs t ds t vsc first cycle v pp h v pp l v pp t wp t dh t a (oe) data c0 16 program address program data t as t ah t wp t ch floating t ds t dh t cs t wp t ch t dp t wrr t a (ce) floating t ds t dh t olz t clz t a (ad) second cycle first cycle second cycle program verify program t wc program data input floating
flash memory version 7751 group users manual 19C14 l erase command figure 19.1.7 shows the erase command and the erase verify command execution timing. ___ the command code is latched into the internal command latch at the rising edge of the we signal by inputting the control signals and the command code 20 16 in the first cycle. ___ the command code is latched into the internal command latch again at the rising edge of the we signal by inputting the control signals and the command code 20 16 again in the second cycle. ___ the erase operation is started at the rising edge of the we signal in the second cycle, and the builtCin flash memory contents are collectively erased within 9.5 ms as measured by the internal timer. write 00 16 to all the builtCin flash memory area before executing the erase command. note: be sure to execute a erase verify command after executing the erase command. if this verification fails, execute repeatedly the erase command and the erase verify command until the verification passes. (refer to 19.1.6 program/erase algorithm flow chart. ) when executing again the erase command after executing the erase verify command and the verification fails, there is no need to write 00 16 to the builtCin flash memory. l erase verify command this command is executed to verify whether or not all contents of the builtCin flash memory have been erased after executing the erase command. ___ the address is latched internally at the falling edge of the we signal by inputting the address, the control signals, and the command code a0 16 in the first cycle. the command code is latched into ___ the internal command latch at the rising edge of the we signal. the data of the specified address (input address) is output to an external by inputting the control signals in the second cycle. 19.1 parallel input/output mode
flash memory version 7751 group users manual 19C15 fig. 19.1.7 erase command and erase verify command execution timing 19.1 parallel input/output mode t rc t wc a 0 Ca 16 ce oe we d 0 Cd 7 t wph t cs 20 16 t df t oh floating verify data output t rrw t ch t cs t ds t vsc first cycle v pp h v pp l v pp t wp t dh t a (oe) a0 16 erase data t wp t ch t ds t dh t cs t wp t ch t de t wrr t a (ce) t ds t dh t olz t clz t a (ad) second cycle erase verify erase verify address t as t ah 20 16 t wc floating first cycle floating floating floating second cycle
flash memory version 7751 group users manual 19C16 19.1 parallel input/output mode l reset command this command is used to stop executing of program or erase safely after inputting the program or erase command code that is, after the command code is latched into the internal command latch in the first cycle. figure 19.1.8 shows the reset command execution timing. when inputting the control signals and the command code ff 16 in the first cycle after the program or erase command code is latched into the command latch, the command code is latched into the ___ internal command latch at the rising edge of the we signal. when inputting the control signals and command code ff 16 again in the second cycle, the command latch is cleared to 00 16 and becomes the state where the read command code is latched. then, program or erase is not executed. (the contents of the builtCin flash memory is not changed.) fig. 19.1.8 reset command execution timing t wc a 0 ? 16 ce oe we d 0 ? 7 t wph t cs 40 16 floating first cycle v pp h v pp l v pp ff 16 t wp t ch t ds t dh ff 16 t dh first cycle second cycle program or erase t wc t cs t wph t wp t ch t ds reset 20 16 or floating floating floating
flash memory version 7751 group users manual 19C17 19.1 parallel input/output mode l device identification command figure 19.1.9 shows the device identification command execution timing. ___ the command code is latched into the internal command latch at the rising edge of the we signal by inputting the control signals and the command code 90 16 in the first cycle. the manufactures code 1c 16 (i.e., mitsubishi) is output externally when inputting an address 00000 16 and the control signals in the second cycle. the device code d0 16 (i.e., 1mCbit flash memory) is output externally when inputting an address 00001 16 and the control signals. floating adi t rc a 0 ? 16 ce oe we d 0 ? 7 t olz t clz t a (ad) t a (oe) 90 16 t df t oh floating ddi output t a (ce) t wc t rrw t ch t wrr t cs t ds data t vsc second cycle first cycle floating v pp h v pp l v pp t wp t dh adi (device identification address) : manufacturer? code 00000 16 ; device code 00001 16 ddi (device identification data) : manufacturer? code 1c 16 ; device code d0 16 fig. 19.1.9 device identification command execution timing
flash memory version 7751 group users manual 19C18 19.1 parallel input/output mode 19.1.5 electrical characteristics dc electrical characteristics (ta = 25 c, v cc = 5 v10%, unless otherwise noted) limits min. max. typ. unit symbol parameter i sb1 i sb2 i cc1 i cc2 i cc3 i pp1 i pp2 i pp3 v pp l v pp h test conditions vcc supply current (at standby) vcc supply current (at read) vcc supply current (at program) vcc supply current (at erase) v pp supply current (at read) v pp supply current (at program) v pp supply current (at erase) v pp supply voltage (read-only mode) v pp supply voltage (read/write mode) ma a ma ma ma a a a ma ma v v vcc = 5.5 v, ce = v ih vcc = 5.5 v, ce = vcc0.2 v vcc = 5.5 v, ce = v il , t rc = 150 ns, iout = 0 ma v pp = v pp h v pp = v pp h 0 v pp vcc+1.0 v v pp = v pp h v pp = v pp h v pp = v pp h 12.0 vcc 11.4 note: v ih /v il , v oh /v ol , and i ih /i il for the control input, address input, and data input/output pins conform to standards for microcomputer modes (memory expansion and microprocessor modes). ac electrical characteristics (ta = 25 c, v cc = 5 v10%, unless otherwise noted) readConly mode parameter ns ns ns ns ns ns ns ns s min. 150 0 0 0 6 limits unit max. 150 150 55 35 symbol read cycle time address access time ___ ce access time ___ oe access time ___ output enable time (after ce) ___ output enable time (after oe) ___ output floating time (after oe) ___ ___ output efficiency time (after ce, oe, address) write recovery time (before read) t rc t a(ad) t a(ce) t a(oe) t clz t olz t df t oh t wrr vcc+1.0 12.6 1 100 30 30 30 10 100 100 30 30
flash memory version 7751 group users manual 19C19 19.1 parallel input/output mode read/write mode parameter ns ns ns ns ns s s ns ns ns ns s ms s min. limits unit max. symbol write cycle time address setup time address hold time data setup time data hold time write recovery time (before read) read recovery time (before write) ___ ce setup time ___ ce hold time write pulse time write pulse waiting time program time erase time v pp setup time t wc t as t ah t ds t dh t wrr t rrw t cs t ch t wp t wph t dp t de t vsc 150 0 60 50 10 6 0 20 0 60 20 10 1 9.5 note: the read timing is same as the read only mode.
flash memory version 7751 group users manual 19C20 19.1.6 program/erase algorithm flow chart 19.1 parallel input/output mode verify byte ? verify byte ? last addr ? no fail increment addr no pass pass fail write read command yes v pp = v pp l device passed device failed duration = 6 x = 1000 ? verify byte ? verify byte ? pass last addr ? no pass write read command yes v pp = v pp l device passed device failed increment addr program v cc = 5v v pp = v pp h addr = first location x = 0 write program write program data duration = 10 s x = x + 1 write program-verify command duration = 6 s x = 25 ? yes start v cc = 5v v pp = v pp h all bytes = 00 16 ? program all bytes = 00 16 addr = first location yes x = 0 write erase command write erase command duration = 9.5 ms x = x + 1 write erase-verify command erase 40 16 c0 16 20 16 20 16 no a0 16 fail no yes fail d in 00 16 00 16 start command s
flash memory version 7751 group users manual 19C21 19.2 serial input/output mode 19.2 serial input/output mode in the serial i/o mode, the contents of the builtCin flash memory can be reprogrammed with the state mounting the microcomputer on the board. 19.2.1 pin description table 19.2.1 lists the pin description in the serial i/o mode.
flash memory version 7751 group users manual 19C22 19.2 serial input/output mode table 19.2.1 pin description in serial i/o mode input/output input input input input output output input input input input input input output i/o input input input input input pin vcc, vss cnvss byte ______ reset x in x out _ e avcc avss v ref p0 0 Cp0 7 p1 0 Cp1 7 p2 0 Cp2 7 p3 0 Cp3 3 p4 0 p4 1 p4 2 p4 3 p4 4 p4 5 p4 6 p4 7 p5 0 p5 1 p5 2 to p5 7 p6 0 to p6 7 p7 0 to p7 7 p8 0 to p8 7 functions supply 5 v 10 % to vcc pin and 0 v to vss pin. supply 12 v 5 %. connect to vss pin or vcc pin. connect to vss pin. connect a ceramic resonator or quartz-crystal oscillator between x in and x out pins. when using an external clock, the clock source must be input to x in pin and x out pin must be left open. h level is output. connect to vcc pin. connect to vss pin. input level between vss and vcc or open. input h or l level, or open. input h or l level, or open. clock f 1 is output. input h or l level, or open. this pin is busy signal output. this pin is serial data i/o. this pin is serial clock input. input h or l level, or open. input h or l level, or open. ___ this pin is oe signal input. input h or l level, or open. input h or l level, or open. name power supply v pp input external data bus width select input reset input clock input clock output enable output analog supply input reference voltage input input port p0 input port p1 input port p2 input port p3 input port p4 busy output sda i/o sclk input input port p4 input port p5 control signal input input port p5 input port p6 input port p7 input port p8
flash memory version 7751 group users manual 19C23 19.2 serial input/output mode 19.2.2 access to builtCin flash memory figure 19.2.1 shows the pin connection in the serial i/o mode. ___ when inputting h level to the sda (p4 5 ), sclk (p4 6 ), and oe signal input (p5 1 ) pins, and after that, applying the v pp h level to the v pp (cnv ss ), the builtCin flash memory operates in the serial i/o mode. the software command, address, and data required for operation of the builtCin flash memory are input/output by the clock synchronous serial transfer in this mode. the software command, address, and program data are taken from sda pin to the inside synchronously with the rising edge of the serial clock inputting to sclk pin. the read data, verify data, and error code are externally output from sda pin synchronously with the falling edge of the serial clock. the transfer is performed at 8Cbit length and lsb first. in the serial i/o mode, the builtCin flash memory is accessed by inputting (execution) of the software command. table 19.2.2 lists the software command. to execute the software command requires twice or four times of the transfer. in the first transfer, the command code is input for selecting the builtCin flash memorys operation. in the second to fourth transfer, address and data etc. are input/output. each software command is described below. as the capacity of the built-in flash memory is 48 kbytes, specify addresses 4000 16 to ffff 16 . if the addresses except addresses 4000 16 to ffff 16 are specified, the error occurs. table 19.2.2 software command and input/output information first transfer (command code input) 00 16 40 16 c0 16 30 16 80 16 software command read program program verify auto erase error check second transfer low-order 8 bits of read address input low-order 8 bits of program address input verify data output 30 16 (command code) input error code output third transfer high-order 8 bits of read address input high-order 8 bits of program address input forth transfer read data output program data input
flash memory version 7751 group users manual 19C24 19.2 serial input/output mode fig. 19.2.1 pin connection in serial i/o mode ] : connect to the oscillation circuit. oe v ss ] sclk sda busy v cc 66 p8 2 /rxd 0 67 p8 1 /clk 0 1 p6 6 /tb1 in 2 p6 5 /tb0 in 3 p6 4 /int 2 4 p6 3 /int 1 5 p6 2 /int 0 6 p6 1 /ta4 in 7 p6 0 /ta4 out 8 p4 1 /rdy 64 p8 4 /cts 1 /rts 1 63 p8 5 /clk 1 62 p8 6 /rxd 1 61 p8 7 /txd 1 60 p0 0 /a 0 59 p0 1 /a 1 58 p0 2 /a 2 57 p0 3 /a 3 9 10 p5 7 /ta3 in 11 p5 6 /ta3 out 12 p5 5 /ta2 in 13 p5 4 /ta2 out 14 p5 3 /ta1 in 15 p5 2 /ta1 out 16 p5 1 /ta0 in 17 p5 0 /ta0 out 18 p4 7 19 p4 6 20 p4 5 21 p4 4 22 p4 3 23 p4 2 / 1 24 56 p0 4 /a 4 55 p0 5 /a 5 54 p0 6 /a 6 53 p0 7 /a 7 52 p1 0 /a 8 /d 8 51 p1 1 /a 9 /d 9 50 p1 2 /a 10 /d 10 49 p1 3 /a 11 /d 11 48 p1 4 /a 12 /d 12 47 p1 5 /a 13 /d 13 46 p1 6 /a 14 /d 14 45 p1 7 /a 15 /d 15 44 p2 0 /a 16 /d 0 43 p2 1 /a 17 /d 1 42 p2 2 /a 18 /d 2 41 p2 3 /a 19 /d 3 80 p7 1 /an 1 79 p7 2 /an 2 78 p7 3 /an 3 77 p7 4 /an 4 76 p7 5 /an 5 75 p7 6 /an 6 74 p7 7 /an 7 /ad trg 73 v ss 72 av ss 71 v ref 70 av cc 69 v cc 68 p8 0 /cts 0 /rts 0 65 p8 3 /txd 0 39 p2 5 /a 21 /d 5 38 p2 6 /a 22 /d 6 25 p4 0 /hold 26 byte 27 cnv ss 28 reset 29 x in 30 x out 31 32 v ss 33 p3 3 /hlda 34 p3 2 /ale 35 p3 1 /bhe 36 p3 0 /r/w 37 p2 7 /a 23 /d 7 40 p2 4 /a 20 /d 4 m37751f6cfp e p7 0 /an 0 p6 7 /tb2 in v pp outline : 80p6n-a (note) note : this pin outputs clock . 1
flash memory version 7751 group users manual 19C25 19.2 serial input/output mode l read command figure 19.2.2 shows the read command execution timing. the command code 00 16 is input at the first transfer. the lowCorder 8 bits and the highCorder 8 bits are input at the second and third transfer. ___ when setting l level to the oe signal, the data of the specified address (input address) is read out and latched up to the internal data latch. ___ when returning h level to the oe signal and inputting the serial clock, the data which is latched up to the data latch is output externally. note: when outputting the read data, the sda pin is switched for output at the first falling edge of the serial clock. the sda pin is placed in the floating state during the t h(c-e) period after the last rising edge of the serial clock (at the 8th bit). t wr read t ch t ch command code input(00 16 ) 00000000 read address input (low-order) a 0 a 7 a 8 a 1 5 d 0 d 7 read data output (note) t cr t rc sclk sda oe busy ? read address input (high-order) fig. 19.2.2 read command execution timing
flash memory version 7751 group users manual 19C26 19.2 serial input/output mode l program command figure 19.2.3 shows the program command execution timing. the command code 40 16 is input at the first transfer. the lowCorder 8 bits and the highCorder 8 bits of the address are input at the second and third transfer. the data is input at the forth transfer. programming is started at the last rising edge of the forth transfer serial clock and the busy signal becomes h level. the input data is programmed to the specified address (input address) within 10 s as measured by the builtCin timer and the busy signal becomes l level. programming is performed by the byte unit. note: be sure to execute a program verify command after executing the program command. if this verification fails, execute repeatedly the program and program verify commands until the verification passes. (refer to 19.2.4 program algorithm flow chart. ) fig. 19.2.3 program command execution timing 00 t ch t ch command code input (40 16 ) 00000 1 program address input (low-order) a 0 a 7 a 8 a 15 d 0 d 7 program data input program t ch t pc t wp sclk sda oe busy ? program address input (high-order)
flash memory version 7751 group users manual 19C27 19.2 serial input/output mode l program verify command figure 19.2.4 shows the program verify command execution timing. this command is executed to verify data of address where the program command has been executed after executing the program command. the command code c0 16 is input at the first transfer. ___ when setting the oe signal to l level, data of address where the program command has been executed is read out and latched to the internal data latch. ___ when returning the oe signal to h level and inputting the serial clock, the data which is latched to the data latch is output externally. since the address is internally latched when the program command is executed, there is no need to input it when the program verify command is executed. fig. 19.2.4 program verify command execution timing 1 000000 verify data output (note) d 0 d 7 command code input (c0 16 ) 1 t crpv sclk sda oe busy t wr t rc verify read note: when outputting the verify data, the sda pin is switched for output at the first falling edge of the serial clock. the sda pin is switched in the floating state during the t h(c-e) period after the last rising edge of the serial clock (at the 8th bit). ?
flash memory version 7751 group users manual 19C28 19.2 serial input/output mode l auto erase command figure 19.2.5 shows the auto erase command execution timing. the command code 30 16 is input at the first transfer. the command code 30 16 is input again at the second transfer. erasing is started at the last rising edge of the second transfer serial clock and the busy signal becomes h level. the busy signal becomes l by erasing all the contents of the builtCin flash memory. note: when executing the auto erase command once, erase ? erase verify is performed repeatedly internally and automatically after programming 00 16 to all memory area until erasing all the contents of the builtCin flash memory. accordingly, erasing is completed by executing the auto erase command once. fig. 19.2.5 auto erase command execution timing 10 t ch command code input (30 16 ) 00001 0 auto erase sclk sda oe busy h t ec 10 command code input (30 16 ) 00001 0
flash memory version 7751 group users manual 19C29 19.2 serial input/output mode l error check command figure 19.2.6 shows the error check command execution timing. the command code 80 16 is input at the first transfer. when inputting the serial clock, the error information is output externally. when an error occurs, the serial communication circuit sets the corresponding error flag to 1 and stops operating, and the serial clock and data are not accepted (even including an error check command). accordingly, apply the v pp l level to the v pp pin to clear the serial i/o mode and then apply the v pp h level again to select the serial i/o mode and initialize the serial communication circuit. the error information is output when first executing the error check command after initializing. figure 19.2.7 shows the error information. the error flag becomes 0 by executing the error check command. be sure to execute the error check command because the error flag is undefined after powerCon. fig. 19.2.6 error check command execution timing 1 0 t ch command code input (80 16 ) 000000 error information output (note) e0e1 ? sclk sda oe busy ? ? ? ? ? ? ? note: when outputting the error information, the sda pin is switched for output at the first falling edge of the serial clock. the sda pin is switched in the floating state during the t h(c-e) period after the last rising edge of the serial clock (at the 8th bit).
flash memory version 7751 group users manual 19C30 19.2 serial input/output mode command error flag (e0) when inputting the code other than the five command codes shown in table 19.2.2, this flag becomes ?.? address error flag (e1) when inputting the addresses other than addresses 4000 16 to ffff 16 , this flag becomes ?. the contents are undefined at reading. ] the error flags are undefined after power-on. ] when executing the error check command, the error flags become ?. fig. 19.2.7 error information
flash memory version 7751 group users manual 19C31 19.2 serial input/output mode 19.2.3 electrical characteristics dc electrical characteristics (ta = 25 c, v cc = 5 v10%, v pp = 12 v5%, unless otherwise noted) limits min. max. typ. unit symbol parameter test conditions vcc = 5.5 v, t wr = 320 ns, i out = 0 ma i cc1 i cc2 i cc3 i pp1 i pp2 i pp3 v pp h vcc supply current (at read) vcc supply current (at program) vcc supply current (at erase) v pp supply current (at read) v pp supply current (at program) v pp supply current (at erase) v pp supply voltage (at serial i/o mode) 30 30 30 100 30 30 12.6 ma ma ma a ma ma v 12.0 11.4 note: v ih /v il , v oh /v ol , and i ih /i il for the control signal input, busy output, sda i/o, and sclk input pins conform to standards for microcomputer modes. ac electrical characteristics (ta = 25 c, v cc = 5 v10%, v pp = 12 v5%, f(x in ) = 40 mhz, unless otherwise noted) parameter ns ns ns ns s s ns ns ns ns ns ns ns ns ns ns ns ns limits unit max. symbol serial transmission interval time read waiting time after transmission read pulse width transfer waiting time after read waiting time before program verify programming time transfer waiting time after programming transfer waiting time after erase sclk input cycle time sclk h pulse width sclk l pulse width sclk rise time sclk fall time sda output delay time sda output hold time sda output hold time (only the 8th bit) sda input setup time sda input hold time t ch t cr t wr t rc t crpv t wp t pc t ec t c(ck) t w(ckh) t w(ckl) t r(ck) t f(ck) t d(c-q) t h(c-q) t h(c-e) t su(d-c) t h(c-d) min. 400 (note 1) 400 (note 1) 320 (note 2) 400 (note 1) 400 (note 1) 400 (note 1) 120 (note 3) 10 90 6 250 100 100 20 20 0 0 30 90 notes 1: when f(x in ) = 25 mhz or less, calculate the minimum value as the following formula 1. 2: when f(x in ) = 25 mhz or less, calculate the minimum value as the following formula 2. 3: when f(x in ) = 25 mhz or less, calculate the minimum value as the following formula 3. 4: when f(x in ) = 25 mhz or less, calculate the maximum value as the following formula 4. formula 1 : formula 2 : formula 4 : formula 3 : 1 5 10 f(x in ) 5 10 9 1 5 8 f(x in ) 5 10 9 1 5 3 f(x in ) 5 10 9 1 5 5 f(x in ) 5 10 9 200 (note 4)
flash memory version 7751 group users manual 19C32 19.2 serial input/output mode timing t c(ck) t w(ckl) t w(ckh) t f (ck) t r (ck) t d (c-q) t h (c-e) t h (c-q) t h (c-d) t su (d-c) test conditions ?utput timing voltage : v ol = 0.8 v, v oh = 2.0 v ?nput timing voltage : v il = 0.2 v cc , v ih = 0.8 v cc sclk sda output sda input
flash memory version 7751 group users manual 19C33 19.2 serial input/output mode 19.2.4 program algorithm flow chart start v cc = 5 v sda = sclk = oe = h v pp = v pp h addr = first location x = 0 write program command write program data duration = 10 s x = x + 1 write program-verify command duration = 6 x = 25 ? verify byte ? verify byte ? last addr ? no yes fail increment addr no pass pass fail write read command yes v pp = v pp l device passed device failed 40 16 c0 16 d in 00 16 s
flash memory version 7751 group users manual 19C34 19.2 serial input/output mode memorandum
appendix appendix 1. memory assignment appendix 2. memory assignment in sfr area appendix 3. control registers appendix 4. package outlines appendix 5. example for processing unused pins appendix 6. hexadecimal instruction code table appendix 7. machine instructions appendix 8. examples of noise immunity improvement appendix 9. q & a
appendix appendix 1. memory assignment 7751 group users manual 20C2 appendix 1. memory assignment 1. during single-chip mode 000000 16 000080 16 004000 16 00ffff 16 00087f 16 m37751m6c-xxxfp m37751e6c-xxxfp m37751e6cfs m37751f6cfp type name sfr area internal ram 2048 bytes not used internal rom 48 kbytes fig. 1. memory assignment during single-chip mode
appendix 1. memory assignment appendix 7751 group users manual 20C3 2. during memory expansion mode fig. 2. memory assignment during memory expansion mode 000000 16 000080 16 004000 16 00ffff 16 00087f 16 sfr area external area internal rom area 48 kbytes internal ram area 2048 bytes external area bank 1 16 bank ff 16 bank 0 16 010000 16 01ffff 16 ff0000 16 ffffff 16 000002 16 sfr area external area 000009 16 m37751m6c-xxxfp m37751e6c-xxxfp m37751e6cfs m37751f6cfp type name
appendix appendix 1. memory assignment 7751 group users manual 20C4 fig. 3. memory assignment during microprocessor mode 3. during microprocessor mode 000000 16 000080 16 00ffff 16 00087f 16 sfr area internal ram area 2048 bytes external area bank 1 16 bank ff 16 bank 0 16 010000 16 01ffff 16 ff0000 16 ffffff 16 000002 16 sfr area external area 000009 16 m37751m6c-xxxfp m37751e6c-xxxfp m37751e6cfs m37751f6cfp type name note: interrupt vector table is assigned to addresses ffd6 16 to ffff 16 . set a rom to this area.
appendix 7751 group users manual 20C5 appendix 2. memory assignment in sfr area appendix 2. memory assignment in sfr area address register name access characteristics state immediately after a reset 10 16 11 16 12 16 13 16 14 16 15 16 16 16 17 16 18 16 19 16 1a 16 1b 16 1c 16 1d 16 1e 16 1f 16 0 16 1 16 2 16 3 16 4 16 5 16 6 16 7 16 8 16 9 16 b 16 c 16 d 16 e 16 f 16 a 16 rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw ? ? 00 16 00 16 ? ? ? 00 16 00 16 ? ? 00 16 0000 00000000 ? 00 16 ? ? ? ? ? ? ? ? ? 00000 ? ? ? ?? 0 0011 ? ? b7 b0 b7 b0 ? 00 16 ? rw rw 00 16 ? : it is possible to read the bit state at reading. the written value becomes valid data. : it is possible to read the bit state at reading. the written value becomes invalid. : the written value becomes valid data. it is impossible to read the bit state. : nothing is assigned. it is impossible to read the bit state. the written value is ignored. rw ro wo access characteristics : 0 immediately after a reset. : 1 immediately after a reset. : undefined immediately after a reset. 0 1 ? : always 0 at reading 0 0 : always undefined at reading : 0 immediately after a reset. fix this bit to 0. ? state immediately after a reset port p8 direction register port p4 register port p5 register port p4 direction register port p5 direction register port p6 register port p7 register port p6 direction register port p7 direction register port p8 register port p0 register port p1 register port p2 register port p3 register port p0 direction register port p1 direction register port p2 direction register port p3 direction register a-d control register 0 a-d control register 1
appendix appendix 2. memory assignment in sfr area 7751 group users manual 20C6 uart1 transmit/receive control register 0 0 20 16 21 16 22 16 23 16 24 16 25 16 26 16 27 16 28 16 29 16 30 16 31 16 32 16 33 16 2b 16 2c 16 2d 16 2e 16 2f 16 2a 16 ro ro ro ro ro rw wo wo ro ro rw b7 b0 ro wo rw ro ro ro rw rw ro ro rw wo wo wo rw rw ro ro ro rw rw ? ? ? ? ? ? ? 0 ??? 1 00 0 ? ? ? 00 16 ? ? ? ? 0000 00 0? ? ? b7 b0 ? 00 16 0000 0 0 1 0 0000 0 0 0 ? 0 ??? 1 00 0 0000 0 0 1 0 ro ro ro ro ro ro ro ro ro ro 000 0 0 0 ? 000 0 0 0 ? 000 0 0 0 ? 000 0 0 0 ? 000 0 0 0 ? 000 0 0 0 ? 000 0 0 0 ? 000 0 0 : it is possible to read the bit state at reading. the written value becomes valid data. : it is possible to read the bit state at reading. the written value becomes invalid. : the written value becomes valid data. it is impossible to read the bit state. : nothing is assigned. it is impossible to read the bit state. the written value is ignored. rw ro wo access characteristics : 0 immediately after a reset. : 1 immediately after a reset. : undefined immediately after a reset. 0 1 ? : always 0 at reading 0 0 : always undefined at reading : 0 immediately after a reset. fix this bit to 0. ? state immediately after a reset register name address access characteristics state immediately after a reset uart0 transmit/receive control register 0 uart0 transmit/receive mode register uart0 baud rate register uart0 transmit buffer register uart1 receive buffer register uart0 transmit/receive control register 1 uart0 receive buffer register uart1 transmit/receive mode register uart1 baud rate register uart1 transmit buffer register uart1 transmit/receive control register 1 a-d register 5 a-d register 1 a-d register 3 a-d register 2 a-d register 4 a-d register 0 a-d register 6 a-d register 7 34 16 35 16 36 16 37 16 38 16 39 16 3a 16 3b 16 3c 16 3d 16 3e 16 3f 16
appendix 7751 group users manual 20C7 appendix 2. memory assignment in sfr area 5c 16 timer b1 mode register 0 40 16 41 16 42 16 43 16 44 16 45 16 46 16 47 16 48 16 49 16 50 16 51 16 52 16 53 16 54 16 55 16 56 16 57 16 58 16 59 16 5a 16 5b 16 5d 16 5e 16 5f 16 4b 16 4c 16 4d 16 4e 16 4f 16 4a 16 wo ] ] ] ] ] ] ] ] rw ] b7 b0 rw ] ] rw rw rw rw rw rw wo rw ? ? ? ? ? ? ? ? ? ? ? ? 00 16 00 16 00 16 00 16 ? 00 16 b7 b0 ? 00 16 00 ?? 0 00 0 0 0 ?? 0 0 0 0 wo rw ] ] ] ] ] rw rw rw rw rw 0000 0 0 0 0 0 0 ?? 0 00 0 000 0 0 0 0 rw rw 00000 0 0 0 0 0 0 0 : it is possible to read the bit state at reading. the written value becomes valid data. : it is possible to read the bit state at reading. the written value becomes invalid. : the written value becomes valid data. it is impossible to read the bit state. : nothing is assigned. it is impossible to read the bit state. the written value is ignored. rw ro wo access characteristics : 0 immediately after a reset. : 1 immediately after a reset. : undefined immediately after a reset. 0 1 ? : always 0 at reading 0 0 : always undefined at reading : 0 immediately after a reset. fix this bit to 0. ? state immediately after a reset register name address access characteristics state immediately after a reset timer b2 register timer a2 register timer a3 register timer a4 register timer b0 register timer b1 register processor mode register 0 one-shot start register timer a0 register up-down register timer a1 register count start register timer a1 mode register timer a2 mode register timer a3 mode register timer b0 mode register timer b2 mode register timer a0 mode register timer a4 mode register processor mode register 1 ? ? ? ? ? ? ] ] ] ] ] ] the access characteristics at addresses 46 16 to 4f 16 varies according to timer as operating mode. (refer to chapter 5. timer a. ) ] the access characteristics at addresses 50 16 to 55 16 varies according to timer bs operating mode. (refer to chapter 6. timer b. ) ] the access characteristics of bit 5 at addresses 5b 16 to 5d 16 varies according to timer bs operating mode. (refer to chapter 6. timer b. ) ] the access characteristics of bit 1 at address 5e 16 and its state immediately after a reset vary according to the voltage level supplied to the cnv ss pin. (refer to section 2.5 processor modes. )
appendix appendix 2. memory assignment in sfr area 7751 group users manual 20C8 timer a0 interrupt control register timer a1 interrupt control register uart1 receive interrupt control register uart0 transmit interrupt control register access characteristics state immediately after a reset watchdog timer frequency select register 60 16 61 16 62 16 63 16 64 16 65 16 66 16 67 16 68 16 69 16 70 16 71 16 72 16 73 16 74 16 75 16 76 16 77 16 78 16 79 16 7a 16 7b 16 7c 16 7d 16 7e 16 7f 16 6b 16 6c 16 6d 16 6e 16 6f 16 6a 16 rw rw rw rw b7 b0 (note 1) rw rw rw rw rw rw rw rw rw rw 0 000 ? 0 ? (note 2) b7 b0 0 0 0 0 0 0 0 0 0 000 00 0 00 0 rw rw 00 0 0 00 0 0 00 0 0 00 0 0 000 0 0 0 0 0 0 0 0 0 00 0 0 00 0 00 0 00 0 00 0 00 0 rw address a-d conversion interrupt control register uart1 transmit interrupt control register int 2 interrupt control register register name watchdog timer register timer a2 interrupt control register timer a3 interrupt control register timer a4 interrupt control register timer b1 interrupt control register timer b2 interrupt control register int 0 interrupt control register timer b0 interrupt control register int 1 interrupt control register notes 1: by writing dummy data to address 60 16 , a value fff 16 is set to the watchdog timer. the dummy data is not retained anywhere. 2: the value fff 16 is set tot the watchdog timer. (refer to chapter 9. watchdog timer. ) uart0 receive interrupt control register ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? : it is possible to read the bit state at reading. the written value becomes valid data. : it is possible to read the bit state at reading. the written value becomes invalid. : the written value becomes valid data. it is impossible to read the bit state. : nothing is assigned. it is impossible to read the bit state. the written value is ignored. rw ro wo access characteristics : 0 immediately after a reset. : 1 immediately after a reset. : undefined immediately after a reset. 0 1 ? : always 0 at reading 0 0 : always undefined at reading : 0 immediately after a reset. fix this bit to 0. ? state immediately after a reset
appendix appendix 3. control registers 7751 group users manual 20C9 appendix 3. control registers the register structure of each control register assignment in the sfr area are shown on the following pages. the view of the register structure is described below. 0 1 0 xxx register (address xx 16 ) b1 b0 b2 b3 b4 b5 b6 b7 0 ] 1 ] 2 ] 3 2 3 ... select bit 0 : ... 1 : ... ... select bit 0 : ... 1 : ... the value is 0 at reading. 0 : ... 1 : ... fix this bit to 0. 4 7 to 5 nothing is assigned. 5 rw wo ro rw rw 0 0 0 bit bit name this bit is ignored in ... mode. functions at reset rw ... flag undefined undefined ] 1 blank : set to 0 or 1 to according to the usage. 0 : set to 0 at writing. 1 : set to 1 at writing. 5 : ignored depending on the specific mode or state. it may be either 0 or 1. : nothing is assigned. ] 2 0 : 0 immediately after a reset. 1 : 1 immediately after a reset. undefined : undefined immediately after a reset. ] 3 rw : it is possible to read the bit state at reading. the written value becomes valid. ro : it is possible to read the bit state at reading. the written value becomes invalid. accordingly, the written value may be 0 or 1. wo : the written value becomes valid. it is impossible to read the bit state. the value is undefined at reading. however, when [0 is at reading] is indicated in the function or note column, the bit is always 0 at reading. (see ] 4 above.) : it is impossible to read the bit state. the value is undefined at reading. however, when [0 is at reading] is indicated in the function or note column, the bit is always 0 at reading. (see ] 4 above.) the written value becomes invalid. accordingly, the written value may be 0 or 1. ] 4 C
appendix appendix 3. control registers 7751 group users manual 20C10 port pi register bit bit name functions 0 1 2 3 4 5 6 7 port pi 0 port pi 2 port pi 3 port pi 4 port pi 6 data is input/output to/from a pin by reading/writing from/to the corres- ponding bit. port pi 5 port pi register (i = 0 to 8) (addresses 2 16 , 3 16 , 6 16 , 7 16 , a 16 , b 16 , e 16 , f 16 , 12 16 ) b1 b0 b2 b3 b4 b5 b6 b7 port pi 1 port pi 7 at reset rw undefined note: bits 7 to 4 of the port p3 register cannot be written and are fixed to 0 at reading. undefined undefined undefined undefined undefined undefined undefined 0 : l level 1 : h level rw rw rw rw rw rw rw rw port pi direction register bit bit name functions 0 1 2 3 4 5 6 7 port pi 0 direction bit port pi 2 direction bit port pi 3 direction bit port pi 4 direction bit port pi 6 direction bit 0 : input mode (functions as an input port) 1 : output mode (functions as an output port) port pi 5 direction bit port pi direction register (i = 0 to 8) (addresses 4 16 , 5 16 , 8 16 , 9 16 , c 16 , d 16 , 10 16 , 11 16 , 14 16 ) b1 b0 b2 b3 b4 b5 b6 b7 port pi 1 direction bit port pi 7 direction bit at reset rw 0 0 0 0 0 0 0 0 rw rw rw rw rw rw rw rw note: bits 7 to 4 of the port p3 direction register cannot be written and are fixed to 0 at reading.
appendix appendix 3. control registers 7751 group users manual 20C11 a-d control register 0 b7 b6 b5 b4 b3 b2 b1 b0 a-d control register 0 (address 1e 16 ) bit a-d conversion frequency ( ad ) select bit 0 a-d conversion start bit trigger select bit 4 a-d operation mode select bit 0 2 1 0 bit name at reset 0 undefined rw functions 0 0 0 : an 0 selected 0 0 1 : an 1 selected 0 1 0 : an 2 selected 0 1 1 : an 3 selected 1 0 0 : an 4 selected 1 0 1 : an 5 selected 1 1 0 : an 6 selected 1 1 1 : an 7 selected (note 2) b2 b1 b0 0 : internal trigger 1 : external trigger 0 0 : one-shot mode 0 1 : repeat mode 1 0 : single sweep mode 1 1 : repeat sweep mode 0 / repeat sweep mode 1 (note 3) 0 : stop a-d conversion 1 : start a-d conversion b4 b3 notes 1: these bits are ignored in the single sweep, repeat sweep mode 0, and repeat sweep mode 1. (they may be either 0 or 1.) 2: when selecting an external trigger, the an 7 pin cannot be used as an analog input pin. 3: use the a-d operation mode select bit 1 (bit 2 at address 1f 16 ) to select either the repeat sweep mode 0 or repeat sweep mode 1. 4: writing to each bit (except bit 6) of the a-d control register 0 must be performed while the a-d converter halts. analog input select bits (valid in one-shot and repeat modes) (note 1) 3 7 6 5 undefined undefined rw rw rw rw rw rw rw rw 0 0 0 0 when a-d conversion frequency ( ad ) select bit 1 (bit 4 at address 1f 16 ) = 0, 0 : f 2 divided by 4, or f 4 divided by 4 1 : f 2 divided by 2, or f 4 divided by 2 when a-d conversion frequency ( ad ) select bit 1 (bit 4 at address 1f 16 ) = 1, 0 : f 2 or f 4 1 : not selected
appendix appendix 3. control registers 7751 group users manual 20C12 a-d control register 1 b7 b6 b5 b4 b3 b2 b1 b0 a-d control register 1 (address 1f 16 ) bit a-d conversion frequency ( ad ) select bit 1 4 a-d operation mode select bit 1 (use in repeat sweep mode 0 and repeat sweep mode 1) (note 4) 2 1 0 bit name at reset 1 undefined rw functions refer to a-d conversion frequency ( ad ) select bit 0 (bit 7 at address 1e 16 ) 0 : repeat sweep mode 0 1 : repeat sweep mode 1 notes 1: these bits are invalid in the one-shot and repeat modes. (they may be either 0 or 1.) 2: when selecting an external trigger, the an 7 pin cannot be used as an analog input pin. 3: analog input pins which are frequently a-d converted are selected in the repeat sweep mode 1. 4: fix this bit to 0 in the one-shot, repeat, and single sweep modes. 5: writing to each bit of the a-d control register 1 must be performed while the a-d converter halts. 3 7 to 5 rw rw 0 0 0 : an 0 , an 1 (2 pins) 0 1 : an 0 to an 3 (4 pins) 1 0 : an 0 to an 5 (6 pins) 1 1 : an 0 to an 7 (8 pins) (note 2) a-d sweep pin select bits (valid in single sweep, repeat sweep mode 0 and repeat sweep mode 1) (note 1) l single sweep mode/repeat sweep mode 0 b1 b0 0 0 : an 0 (1 pin) 0 1 : an 0 , an 1 (2 pins) 1 0 : an 0 to an 2 (3 pins) 1 1 : an 0 to an 3 (4 pins) l repeat sweep mode 1 (note 3) b1 b0 1 rw 8/10-bit mode select bit 0 : 8-bit mode 1 : 10-bit mode rw 0 nothing is assigned. rw 0 C
appendix appendix 3. control registers 7751 group users manual 20C13 a-d register i b7 b0 a-d register 0 (addresses 21 16 , 20 16 ) a-d register 1 (addresses 23 16 , 22 16 ) a-d register 2 (addresses 25 16 , 24 16 ) a-d register 3 (addresses 27 16 , 26 16 ) a-d register 4 (addresses 29 16 , 28 16 ) a-d register 5 (addresses 2b 16 , 2a 16 ) a-d register 6 (addresses 2d 16 , 2c 16 ) a-d register 7 (addresses 2f 16 , 2e 16 ) bit 7 to 0 at reset 0 undefined rw functions ro b7 b0 (b15) (b8) reads an a-d conversion result. 15 to 8 the value is 0 at reading. l 8-bit mode b7 b0 a-d register 0 (addresses 21 16 , 20 16 ) a-d register 1 (addresses 23 16 , 22 16 ) a-d register 2 (addresses 25 16 , 24 16 ) a-d register 3 (addresses 27 16 , 26 16 ) a-d register 4 (addresses 29 16 , 28 16 ) a-d register 5 (addresses 2b 16 , 2a 16 ) a-d register 6 (addresses 2d 16 , 2c 16 ) a-d register 7 (addresses 2f 16 , 2e 16 ) bit 9 to 0 at reset 0 undefined rw functions ro b7 b0 (b15) (b8) reads an a-d conversion result. 15 to 10 l 10-bit mode b2 (b10) ro ro the value is 0 at reading.
appendix appendix 3. control registers 7751 group users manual 20C14 uarti transmit/receive mode register uarti baud rate register (brgi) b7 b6 b5 b4 b3 b2 b1 b0 bit 4 2 1 0 bit name at reset 0 rw functions b2 b1 b0 3 7 6 5 rw rw rw rw rw rw rw rw 0 0 0 0 serial i/o mode select bits 0 0 0 : serial i/o disabled (p8 functions as a programmable i/o port.) 0 0 1 : clock synchronous serial i/o mode 0 1 0 : not selected 0 1 1 : not selected 1 0 0 : uart mode (transfer data length = 7 bits) 1 0 1 : uart mode (transfer data length = 8 bits) 1 1 0 : uart mode (transfer data length = 9 bits) 1 1 1 : not selected sleep select bit (valid in uart mode) ( note ) parity enable bit (valid in uart mode) ( note ) odd/even parity select bit (valid in uart mode when parity enable bit is 1) ( note ) stop bit length select bit (valid in uart mode) ( note ) internal/external clock select bit uart0 transmit/receive mode register (address 30 16 ) uart1 transmit/receive mode register (address 38 16 ) note: bits 4 to 6 are ignored in the clock synchronous serial i/o mode. (they may be either 0 or 1.) additionally, fix bit 7 to 0. 0 : odd parity 1 : even parity 0 : parity disabled 1 : parity enabled 0 : sleep mode cleared (ignored) 1 : sleep mode selected 0 : internal clock 1 : external clock 0 : one stop bit 1 : two stop bits 0 0 0 b7 b0 uart0 baud rate register (address 31 16 ) uart1 baud rate register (address 39 16 ) functions bit at reset rw 7 to 0 can be set to 00 16 to ff 16 . assuming that the set value = n, brgi divides the count source frequency by n + 1. undefined wo
appendix appendix 3. control registers 7751 group users manual 20C15 uarti transmit buffer register uarti transmit/receive control register 0 b7 b0 bit 8 to 0 at reset undefined rw functions wo b7 b0 (b15) (b8) 15 to 9 C undefined uart0 transmit buffer register (addresses 33 16 , 32 16 ) uart1 transmit buffer register (addresses 3b 16 , 3a 16 ) nothing is assigned. transmit data is set. cts/rts select bit bit 1 brg count source select bits bit name at reset rw functions b7 b6 b5 b4 b3 b2 b1 b0 0 0 : f 2 / f 4 0 1 : f 16 / f 32 1 0 : f 64 / f 128 1 1 : f 512 / f 1024 uart0 transmit/receive control register 0 (address 34 16 ) uart1 transmit/receive control register 0 (address 3c 16 ) b1 b0 0 : cts function selected. 1 : rts function selected. transmit register empty flag 0 : data present in transmit register. (during transmitting) 1 : no data present in transmit register. (transmitting completed) 1 0 0 0 7 0 : lsb (least significant bit) first 1 : msb (most significant bit) first 0 transfer format select bit (used in clock synchronous serial i/o mode) (note) 0 2 rw rw ro 3 rw 6 to 4 nothing is assigned. undefined C rw note: fix bit 7 to 0 in the uart mode or when serial i/o is ignored.
appendix appendix 3. control registers 7751 group users manual 20C16 uarti transmit/receive control register 1 uarti receive buffer register bit bit name at reset 5 framing error flag (valid in uart mode) 0 0 : no framing error 1 : framing error detected rw functions b7 b6 b5 b4 b3 b2 b1 b0 uart0 transmit/receive control register 1 (address 35 16 ) uart1 transmit/receive control register 1 (address 3d 16 ) notes 1: bit 4 is cleared to 0 when clearing the receive enable bit to 0. bits 5 and 6 are cleared to 0 when one of the following is performed: ?clearing the receive enable bit to 0. ?reading the low-order byte of the uarti receive buffer register (addresses 36 16 , 3e 16 ) out . bit 7 is cleared to 0 when all of bits 4 to 6 become 0. 2: bits 5 to 7 are ignored in the clock synchronous serial i/o mode. 0 transmit enable bit 0 0 : transmission disabled 1 : transmission enabled 1 transmit buffer empty flag 1 0 : data present in transmit buffer register. 1 : no data present in transmit buffer register. 2 receive enable bit 0 0 : reception disabled 1 : reception enabled 3 receive complete flag 0 0 : no data present in receive buffer register. 1 : data present in receive buffer register. 4 overrun error flag 0 0 : no overrun error 1 : overrun error detected 6 parity error flag (valid in uart mode) 0 0 : no parity error 1 : parity error detected 7 error sum flag (valid in uart mode) 0 0 : no error 1 : error detected (notes 1, 2) (notes 1, 2) (notes 1, 2) (note 1) rw ro rw ro ro ro ro ro b7 b0 bit 8 to 0 at reset undefined rw functions ro b7 b0 (b15) (b8) 15 to 9 C uart0 receive buffer register (addresses 37 16 , 36 16 ) uart1 receive buffer register (addresses 3f 16 , 3e 16 ) nothing is assigned. the value is 0 at reading. receive data is read out from here. 0
appendix appendix 3. control registers 7751 group users manual 20C17 count start register one-shot start register bit timer b2 count start bit timer b1 count start bit timer b0 count start bit timer a4 count start bit timer a3 count start bit timer a2 count start bit timer a1 count start bit timer a0 count start bit bit name at reset 0 0 0 0 0 0 0 0 rw functions b7 b6 b5 b4 b3 b2 b1 b0 count start register (address 40 16 ) 0 : stop counting 1 : start counting rw rw rw rw rw rw rw rw 0 1 2 3 4 5 6 7 bit 7 to 5 nothing is assigned. timer a4 one-shot start bit timer a3 one-shot start bit timer a2 one-shot start bit timer a1 one-shot start bit timer a0 one-shot start bit bit name at reset 0 0 undefined 0 0 0 rw functions b7 b6 b5 b4 b3 b2 b1 b0 one-shot start register (address 42 16 ) 1 : start outputting one-shot pulse (valid when selecting internal trigger.) the value is 0 at reading. 0 1 2 3 4 wo wo wo wo wo C
appendix appendix 3. control registers 7751 group users manual 20C18 up-down register bit bit name at reset 0 0 0 0 0 rw functions b7 b6 b5 b4 b3 b2 b1 b0 up-down register (address 44 16 ) 0 0 0 timer a4 up-down bit timer a3 up-down bit timer a2 up-down bit timer a1 up-down bit timer a0 up-down bit timer a2 two-phase pulse signal processing select bit (note) timer a3 two-phase pulse signal processing select bit (note) timer a4 two-phase pulse signal processing select bit (note) 0 : down-count 1 : up-count this function is valid when the contents of the up-down register is selected as the up-down switching factor. 0 : two-phase pulse signal processing function disabled 1 : two-phase pulse signal processing function enabled when not using the two-phase pulse signal processing function, set the bit to ?. the value is ??at reading. note: use the ldm or sta instruction when writing to bits 5 to 7. 0 1 2 3 4 5 6 7 rw rw rw rw rw wo wo wo
appendix appendix 3. control registers 7751 group users manual 20C19 timer ai register timer ai mode register b7 b0 b7 b0 (b15) (b8) timer a0 register (addresses 47 16 , 46 16 ) timer a1 register (addresses 49 16 , 48 16 ) timer a2 register (addresses 4b 16 , 4a 16 ) timer a3 register (addresses 4d 16 , 4c 16 ) timer a4 register (addresses 4f 16 , 4e 16 ) functions bit at reset rw 15 to 0 these bits have different functions according to the operating mode. undefined rw bit 7 5 4 3 1 bit name at reset 0 0 0 0 0 0 0 0 rw functions b7 b6 b5 b4 b3 b2 b1 b0 timer ai mode register (i = 0 to 4) (addresses 56 16 to 5a 16 ) 0 0 : timer mode 0 1 : event counter mode 1 0 : one-shot pulse mode 1 1 : pulse width modulation (pwm) mode b1 b0 these bits have different functions according to the operating mode. operating mode select bits 6 2 0 rw rw rw rw rw rw rw rw
appendix appendix 3. control registers 7751 group users manual 20C20 timer mode b7 b0 b7 b0 (b15) (b8) timer a0 register (addresses 47 16 , 46 16 ) timer a1 register (addresses 49 16 , 48 16 ) timer a2 register (addresses 4b 16 , 4a 16 ) timer a3 register (addresses 4d 16 , 4c 16 ) timer a4 register (addresses 4f 16 , 4e 16 ) functions bit at reset rw 15 to 0 these bits can be set to 0000 16 to ffff 16 . assuming that the set value = n, the counter divides the count source frequency by n + 1. when reading, the register indicates the counter value. undefined rw gate function select bits pulse output function select bit 1 operating mode select bits bit name functions b7 b6 b5 b4 b3 b2 b1 b0 timer ai mode register (i = 0 to 4) (addresses 56 16 to 5a 16 ) 0 0 : timer mode 0 : no pulse output (tai out pin functions as a programmable i/o port.) 1 : pulse output (tai out pin functions as a pulse output pin.) 0 0 : f 2 / f 4 0 1 : f 16 / f 32 1 0 : f 64 / f 128 1 1 : f 512 / f 1024 b7 b6 count source select bits b1 b0 b4 b3 0 0 0 0 : no gate function 0 1 : (tai in pin functions as a prog- rammable i/o port.) 1 0 : counter counts only while tai in pins input signal is l level. 1 1 : counter counts only while tai in pins input signal is h level. bit 4 at reset rw 0 2 0 rw 0 rw 0 rw 3 0 rw 0 rw 5 0 rw 6 7 0 rw 0 rw 0 fix this bit to 0 in the timer mode.
appendix appendix 3. control registers 7751 group users manual 20C21 event counter mode b7 b6 b5 b4 b3 b2 b1 b0 001 bit up-down switching factor select bit count polarity select bit bit name these bits are ignored in event counter mode. fix this bit to ??in event counter mode. 5 : it may be either ??or ?. 7 functions 0 : counts at falling edge of external signal 1 : counts at rising edge of external signal 0 : contents of up-down register 1 : input signal to tai out pin at reset 0 0 0 0 0 rw pulse output function select bit operating mode select bits 1 0 : no pulse output (tai out pin functions as a programmable i/o port.) 1 : pulse output (tai out pin functions as a pulse output pin.) 0 1 : event counter mode b1 b0 0 0 0 55 0 2 rw rw 3 4 5 6 rw rw rw rw rw rw timer ai mode register (i = 0 to 4) (addresses 56 16 to 5a 16 ) b7 b0 b7 b0 (b15) (b8) timer a0 register (addresses 47 16 , 46 16 ) timer a1 register (addresses 49 16 , 48 16 ) timer a2 register (addresses 4b 16 , 4a 16 ) timer a3 register (addresses 4d 16 , 4c 16 ) timer a4 register (addresses 4f 16 , 4e 16 ) rw 15 to 0 bit functions at reset rw these bits can be set to ?000 16 ?to ?fff 16 . assuming that the set value = n, the counter divides the count source frequency by n + 1 when down-counting, or by ffff 16 ?n + 1 when up-counting. when reading, the register indicates the counter value. undefined
appendix appendix 3. control registers 7751 group users manual 20C22 one-shot pulse mode b7 b0 b7 b0 (b15) (b8) timer a0 register (addresses 47 16 , 46 16 ) timer a1 register (addresses 49 16 , 48 16 ) timer a2 register (addresses 4b 16 , 4a 16 ) timer a3 register (addresses 4d 16 , 4c 16 ) timer a4 register (addresses 4f 16 , 4e 16 ) rw 15 to 0 these bits can be set to 0000 16 to ffff 16 . assuming that the set value = n, the h level width of the one-shot pulse output from the tai out pin is expressed as follows : undefined f i : frequency of count source (f 2 / f 4 , f 16 / f 32 , f 64 / f 128 , or f 512 / f 1024 ) wo trigger select bits fix this bit to 1 in one-shot pulse mode. 1 @ bit name functions b7 b6 b5 b4 b3 b2 b1 b0 timer ai mode register (i = 0 to 4) (addresses 56 16 to 5a 16 ) 1 0 : one-shot pulse mode 7 0 0 : f 2 / f 4 0 1 : f 16 / f 32 1 0 : f 64 / f 128 1 1 : f 512 / f 1024 b7 b6 count source select bits b1 b0 b4 b3 fix this bit to 0 in one-shot pulse mode. 10 1 0 0 : writing 1 to one-shot start register 0 1 : (tai in pin functions as a prog- rammable i/o port.) 1 0 : falling edge of tai in pins input signal 1 1 : rising edge of tai in pins input signal bit at reset 0 0 0 0 0 0 0 0 rw 0 4 0 2 3 5 6 rw rw rw rw rw rw rw rw operating mode select bits n f i . bit functions at reset
appendix appendix 3. control registers 7751 group users manual 20C23 pulse width modulation (pwm) mode b7 b0 b7 b0 timer a0 register (addresses 47 16 , 46 16 ) timer a1 register (addresses 49 16 , 48 16 ) timer a2 register (addresses 4b 16 , 4a 16 ) timer a3 register (addresses 4d 16 , 4c 16 ) timer a4 register (addresses 4f 16 , 4e 16 ) functions bit at reset rw 15 to 0 these bits can be set to 0000 16 to fffe 16 . assuming that the set value = n, the h level width of the pwm pulse output from the tai out pin is expressed as follows: undefined (b15) (b8) wo n f i f i : frequency of count source (f 2 / f 4 , f 16 / f 32 , f 64 / f 128 , or f 512 / f 1024 ) (b15) b7 b0 b7 b0 (b8) timer a0 register (addresses 47 16 , 46 16 ) timer a1 register (addresses 49 16 , 48 16 ) timer a2 register (addresses 4b 16 , 4a 16 ) timer a3 register (addresses 4d 16 , 4c 16 ) timer a4 register (addresses 4f 16 , 4e 16 ) functions bit at reset rw 7 to 0 15 to 8 undefined undefined these bits can be set to 00 16 to ff 16 . assuming that the set value = m, pwm pulses period output from the tai out pin is expressed as follows: (m + 1)(2 8 C 1) f i wo these bits can be set to 00 16 to fe 16 . assuming that the set value = n, the h level width of the pwm pulse output from the tai out pin is expressed as follows: n(m + 1) f i wo f i : frequency of count source (f 2 / f 4 , f 16 / f 32 , f 64 / f 128 , or f 512 / f 1024 ) b7 b6 b5 b4 b3 b2 b1 b0 timer ai mode register (i = 0 to 4) (addresses 56 16 to 5a 16 ) 7 0 0 : f 2 / f 4 0 1 : f 16 / f 32 1 0 : f 64 / f 128 1 1 : f 512 / f 1024 b7 b6 count source select bits 11 1 at reset 0 rw trigger select bits fix this bit to 1 in pwm mode. 1 operating mode select bits bit name functions 1 1 : pwm mode b1 b0 b4 b3 16/8-bit pwm mode select bit 0 0 : writing 1 to count start register 0 1 : (tai in pin functions as a pro- grammable i/o port.) 1 0 : falling edge of tai in pins input signal 1 1 : rising edge of tai in pins input signal bi t 0 : as a 16-bit pulse width modulator 1 : as an 8-bit pulse width modulator 4 0 2 3 5 6 0 0 0 0 0 0 0 rw rw rw rw rw rw rw rw
appendix appendix 3. control registers 7751 group users manual 20C24 timer bi register timer bi mode register b7 b0 b7 b0 (b15) (b8) timer b0 register (addresses 51 16 , 50 16 ) timer b1 register (addresses 53 16 , 52 16 ) timer b2 register (addresses 55 16 , 54 16 ) functions bit at reset rw 15 to 0 these bits have different functions according to the operating mode. undefined rw nothing is assigned. these bits have different functions according to the operating mode. 1 operating mode select bits bit name functions b7 b6 b5 b4 b3 b2 b1 b0 timer bi mode register (i = 0 to 2) (addresses 5b 16 to 5d 16 ) 0 0 : timer mode 0 1 : event counter mode 1 0 : pulse period/pulse width measurement mode 1 1 : not selected b1 b0 bit 5 at reset rw 0 2 0 rw rw rw 6 7 note: bit 5 is ignored in the timer and event counter modes; its value is undefined at reading. 3 0 0 rw 0 C undefined 4 ro (note) undefined rw 0 rw 0 these bits have different functions according to the operating mode.
appendix appendix 3. control registers 7751 group users manual 20C25 timer mode b7 b6 b5 b4 b3 b2 b1 b0 00 bit this bit is ignored in timer mode. nothing is assigned. bit name count source select bits 5 : it may be either ??or ?. functions at reset rw these bits are ignored in timer mode. operating mode select bits 1 0 0 : timer mode b1 b0 0 5 5 0 2 rw rw 3 rw rw timer bi mode register (i = 0 to 2) (addresses 5b 16 to 5d 16 ) 5 0 0 0 undefined 4 undefined 5 6 7 0 0 : f 2 /f 4 0 1 : f 16 /f 32 1 0 : f 64 /f 128 1 1 : f 512 /f 1024 b7 b6 rw 0 rw 0 b7 b0 b7 b0 (b15) (b8) timer b0 register (addresses 51 16 , 50 16 ) timer b1 register (addresses 53 16 , 52 16 ) timer b2 register (addresses 55 16 , 54 16 ) rw 15 to 0 bit functions at reset these bits can be set to ?000 16 ?to ?fff 16 . assuming that the set value = n, the counter divides the count source frequency by n + 1. when reading, the register indicates the counter value. undefined rw
appendix appendix 3. control registers 7751 group users manual 20C26 event counter mode b7 b0 b7 b0 (b15) (b8) timer b0 register (addresses 51 16 , 50 16 ) timer b1 register (addresses 53 16 , 52 16 ) timer b2 register (addresses 55 16 , 54 16 ) rw 15 to 0 bit functions at reset rw these bits can be set to ?000 16 ?to ?fff 16 . assuming that the set value = n, the counter divides the count source frequency by n + 1. when reading, the register indicates the counter value. undefined 0 0 : count at falling edge of external signal 0 1 : count at rising edge of external signal 1 0 : counts at both falling and rising edges of external signal 1 1 : not selected b7 b6 b5 b4 b3 b2 b1 b0 01 bit count polarity select bit bit name these bits are ignored in event counter mode. this bit is ignored in event counter mode. 5 : it may be either ??or ?. 7 functions at reset 0 0 0 rw operating mode select bits 1 0 1 : event counter mode b1 b0 0 0 0 55 0 2 rw rw 3 4 5 6 rw rw rw rw timer bi mode register (i = 0 to 2) (addresses 5b 16 to 5d 16 ) b3 b2 nothing is assigned. 5 undefined undefined
appendix appendix 3. control registers 7751 group users manual 20C27 pulse period/pulse width measurement mode measurement mode select bits 1 operating mode select bits bit name functions b7 b6 b5 b4 b3 b2 b1 b0 timer bi mode register (i = 0 to 2) (addresses 5b 16 to 5d 16 ) 1 0 : pulse period/pulse width measurement mode 7 0 0 : f 2 / f 4 0 1 : f 16 / f 32 1 0 : f 64 / f 128 1 1 : f 512 / f 1024 b7 b6 count source select bits b1 b0 b3 b2 nothing is assigned. 0 1 0 0 : pulse period measurement (interval between falling edges of measurement pulse) 0 1 : pulse period measurement (interval between rising edges of measurement pulse) 1 0 : pulse width measurement (interval from a falling edge to a rising edge, and from a rising edge to a falling edge of measurement pulse) 1 1 : not selected bit at reset undefined 0 rw 4 0 2 3 6 rw rw rw rw C rw rw b7 b0 b7 b0 (b15) (b8) timer b0 register (addresses 51 16 , 50 16 ) timer b1 register (addresses 53 16 , 52 16 ) timer b2 register (addresses 55 16 , 54 16 ) functions bit rw 15 to 0 the measurement result of pulse period or pulse width is read out. undefined ro 5 0 0 0 timer bi overflow flag (note) 0 : no overflow 1 : overflowed undefined ro 0 0 note: the timer bi overflow flag is cleared to 0 by writing to the timer bi mode register with the count start bit = 1. the timer bi overflow flag cannot be set to 1 by software. at reset
appendix appendix 3. control registers 7751 group users manual 20C28 processor mode register 0 bit bit name functions at reset rw 0 1 2 3 4 5 6 7 processor mode bits software reset bit interrupt priority detection time select bits clock 1 output select bit (note 2) 0 0 0 0 0 0 : single-chip mode 0 1 : memory expansion mode 1 0 : microprocessor mode 1 1 : not selected the microcomputer is reset by writing 1 to this bit. the value is 0 at reading. 0 0 : 7 cycles of 0 1 : 4 cycles of 1 0 : 2 cycles of 1 1 : not selected 0 : clock 1 output disabled (p4 2 functions as a programmable i/o port.) 1 : clock 1 output enabled (p4 2 functions as a clock 1 out- put pin.) 0 0 b1 b0 b5 b4 processor mode register 0 (address 5e 16 ) (note 1) notes 1: while supplying the vcc level to the cnvss pin, this bit becomes 1. (fixed to 1.) 2: this bit is ignored in the microprocessor mode. (it may be either 0 or 1.) b1 b0 b2 b3 b4 b5 b6 b7 0 rw rw fix this bit to 0. rw wo 0 rw 0 rw fix this bit to 0. rw rw 0
appendix appendix 3. control registers 7751 group users manual 20C29 processor mode register 1 b7 b6 b5 b4 b3 b2 b1 b0 processor mode register 1 (address 5f 16 ) bit 5 bus cycle select bits 3 2 1, 0 bit name at reset 0 rw functions in high-speed running 0 0 : 5 access in high-speed running 0 1 : 4 access in high-speed running 1 0 : 3 access in high-speed running 1 1 : not selected note: fix this bit to 0 when f(x in ) > 25 mhz. fix these bits to 0. 4 7, 6 rw rw rw rw 0 0 0 clock source for peripheral devices select bit (note) 0 : divided by 2 1 : cpu running speed select bit (note) 0 : high-speed running 1 : low-speed running rw 0 rw 0 b5 b4 in low-speed running 0 0 : not selected 0 1 : 4 access in low-speed running 1 0 : 3 access in low-speed running 1 1 : 2 access in low-speed running b5 b4 fix these bits to 0. 000 0
appendix appendix 3. control registers 7751 group users manual 20C30 watchdog timer register b7 b0 watchdog timer register (address 60 16 ) bit initializes the watchdog timer. when a dummy data is written to this register, the watchdog timer? value is initialized to ?ff 16 .?(dummy data: 00 16 to ff 16 ) at reset undefined rw functions 7 to 0 watchdog timer frequency select register 0 : wf 512 / wf 1024 1 : wf 32 / wf 64 at reset undefined 0 rw functions b7 b6 b5 b4 b3 b2 b1 b0 watchdog timer frequency select register (address 61 16 ) bit nothing is assigned. watchdog timer frequency select bit bit name 0 7 to 1 rw
appendix appendix 3. control registers 7751 group users manual 20C31 interrupt control register b7 b6 b5 b4 b3 b2 b1 b0 a-d conversion, uart0 and 1 transmit, uart0 and 1 receive, timers a0 to a4, timers b0 to b2 interrupt control registers (addresses 70 16 to 7c 16 ) bit 7 to 4 interrupt request bit 2 1 0 bit name at reset 0 rw functions 0 0 0 : level 0 (interrupt disabled) 0 0 1 : level 1 low level 0 1 0 : level 2 0 1 1 : level 3 1 0 0 : level 4 1 0 1 : level 5 1 1 0 : level 6 1 1 1 : level 7 high level b2 b1 b0 0 : no interrupt request 1 : interrupt request interrupt priority level select bits 3 rw rw rw rw undefined 0 0 0 nothing is assigned. note: the a-d conversion interrupt request bit becomes undefined after reset. (note) b7 b6 b5 b4 b3 b2 b1 b0 int 0 to int 2 interrupt control registers (addresses 7d 16 to 7f 16 ) bit 4 interrupt request bit (note) 2 1 0 bit name at reset 0 rw functions 0 0 0 : level 0 (interrupt disabled) 0 0 1 : level 1 low level 0 1 0 : level 2 0 1 1 : level 3 1 0 0 : level 4 1 0 1 : level 5 1 1 0 : level 6 1 1 1 : level 7 high level b2 b1 b0 0 : no interrupt request 1 : interrupt request 0 : edge sense 1 : level sense note: the int 0 to int 2 interrupt request bits are invalid when selecting the level sense. interrupt priority level select bits 3 7, 6 5 rw rw rw rw rw rw 0 0 undefined 0 0 0 polarity select bit 0 : set the interrupt request bit at ??level for level sense and at falling edge for edge sense. 1 : set the interrupt request bit at ??level for level sense and at rising edge for edge sense. level sense/edge sense select bit nothing is assigned.
appendix 7751 group users manual 20C32 appendix 4. package outlines appendix 4. package outlines 80p6n-a
appendix 7751 group users manual 20C33 appendix 4. package outlines 80d0
appendix 7751 group users manual 20C34 appendix 5. example for processing unused pins appendix 5. example for processing unused pins table 1 example for processing unused pins in single-chip mode example of processing set for input mode and connect these pins to vcc or vss via a resistor; or set for output mode and leave these pins open. (note 1) leave it open. connect this pin to vcc. connect these pins to vss. pin name ports p0 to p8 _ e x out (note 2) avcc avss, v ref , byte notes 1: when setting these ports to the output mode and leave them open, they remain set to the input mode until they are switched to the output mode by software after reset. while ports remain set to the input mode, consequently, voltage levels of pins are unstable, and a power source current can increase. the contents of the direction register can be changed by noise or a program runaway generated by noise. to improve its reliability, we recommend to periodically set the contents of the direction register by software. when processing unused pins, use the possible shortest wiring (within 20 mm from the microcomputer). 2: this applies when a clock externally generated is input to the x in pin.
appendix 7751 group users manual 20C35 appendix 5. example for processing unused pins table 2 example for processing unused pins in memory expansion mode or microprocessor mode pin name ports p4 2 to p4 7 , p5 to p8 ____ bhe ( note 2 ) ale ( note 3 ) _____ hlda, f 1 x out ( note 5 ) _____ ____ hold, rdy avcc avss, v ref example of processing set for input mode and connect these pins to vcc or vss via a resistor; or set for output mode and leave these pins open. (note 1) leave them open. (note 4) leave it open. connect these pins to vcc via a resistor (pull-up). connect this pin to vcc. connect these pins to vss. notes 1: when setting these ports to the output mode and leave them open, they remain set to the input mode until they are switched to the output mode by software after reset. while ports remain set to the input mode, consequently, voltage levels of pins are unstable, and a power source current can increase. the contents of the direction register can be changed by noise or a program runaway generated by noise. to improve its reliability, we recommend to periodically set the contents of the direction register by software. when processing unused pins, use the possible shortest wiring (within 20 mm from the microcomputer). 2: this applies when h level is input to the byte pin. 3: this applies when h level is input to the byte pin and the access space is 64 kbytes. 4: when supplying vss level to the cnvss pin, these pins remain set to the input mode until they are switched to the output mode by software after reset (until the pin function is switched in the case of the f 1 pin in the memory expansion mode). while pins remain set to the input mode, consequently, voltage levels of pins are unstable, and a power source current can increase. 5: this applies when a clock externally generated is input to the x in pin.
appendix 7751 group users manual 20C36 appendix 5. example for processing unused pins fig. 4. example for processing unused pins p0Cp8 m37751 v ss av cc e x out p4 2 Cp4 7 , p5Cp8 1 av ss v ref hold rdy m37751 v cc v ss av cc x out bhe ale v cc in single-chip mode p0Cp8 av ss v ref byte m37751 v ss av cc e x out p4 2 Cp4 7 , p5Cp8 1 av ss v ref hold rdy m37751 v ss av cc in memory expansion mode and microprocessor mode x out ale v cc v cc l when setting ports for input mode l when setting ports for output mode left open byte v ref av ss left open left open hlda in memory expansion mode in microprocessor mode in single-chip mode left open left open bhe hlda left open left open left open
appendix 7751 group user? manual 20?7 appendix 6. hexadecimal instruction code table appendix 6. hexadecimal instruction code table
appendix 7751 group users manual 20C38 appendix 6. hexadecimal instruction code table
appendix 7751 group users manual 20C39 appendix 6. hexadecimal instruction code table
appendix 7751 group user? manual 20?0 appendix 7. machine instructions appendix 7. machine instructions
appendix 7751 group users manual 20C41 appendix 7. machine instructions
appendix 7751 group users manual 20C42 appendix 7. machine instructions
appendix 7751 group users manual 20C43 appendix 7. machine instructions
appendix 7751 group users manual 20C44 appendix 7. machine instructions
appendix 7751 group users manual 20C45 appendix 7. machine instructions
appendix 7751 group users manual 20C46 appendix 7. machine instructions
appendix 7751 group users manual 20C47 appendix 7. machine instructions
appendix 7751 group users manual 20C48 appendix 7. machine instructions
appendix 7751 group users manual 20C49 appendix 7. machine instructions
appendix 7751 group users manual 20C50 appendix 7. machine instructions
appendix 7751 group users manual 20C51 appendix 7. machine instructions
appendix 7751 group users manual 20C52 appendix 7. machine instructions
appendix 7751 group users manual 20C53 appendix 7. machine instructions
appendix 7751 group users manual 20C54 appendix 7. machine instructions
appendix 7751 group users manual 20C55 appendix 7. machine instructions
appendix 7751 group users manual 20C56 appendix 7. machine instructions
appendix 7751 group users manual 20C57 appendix 7. machine instructions
appendix 7751 group users manual 20C58 appendix 7. machine instructions
appendix 7751 group users manual 20C59 appendix 7. machine instructions
appendix 7751 group users manual 20C60 appendix 7. machine instructions
7751 group users manual 20C61 appendix appendix 8. examples of noise immunity improvement appendix 8. examples of noise immunity improvement generally effective examples of noise immunity improvements are described below. although the effect of these countermeasure depends on each system, refer to the following when an noise-related problem occurs. 1. short wiring length the wiring on a printed circuit board may function as an antenna which feeds noise into the microcomputer. the shorter the total wiring length (by mm unit), the less possibility of noise insertion into the microcomputer. (1) ______ wiring for reset pin ______ make the length of wiring connected to reset pin as short as possible. ______ in particular, connect a capacitor between reset pin and vss pin with the shortest possible wiring (within 20 mm). ______ fig. 5. wiring for reset pin reason: ______ if noise is input to reset pin, the microcomputer restarts operat- ion before the internal state of the microcomputer is completely initialized. this may cause a program runaway. reset reset circuit noise vss vss m37751 reset circuit vss reset vss m37751 a c c e p t a b l e n o t a c c e p t a b l e
7751 group users manual 20C62 appendix appendix 8. examples of noise immunity improvement (2) wiring for clock input/output pins make the length of wiring connected to the clock input/output pins as short as possible. make the length of wiring between the grounding lead of the capacitor, which is connected to the oscillator and vss pin of the microcomputer, as short as possible (within 20 mm). separate the vss pattern for oscillation from all other vss patterns. (refer to figure 14.) reason: the microcomputers operation synchronizes with a clock generated by the oscillation circuit. if noise enters clock i/o pins, clock waveforms may be deformed. this may cause a malfunction or a program runaway. also, if the noise causes a potential difference between the vss level of the microcomputer and the vss level of an oscillator, the correct clock will not be input in the microcomputer. (3) wiring for cnvss pin connect cnvss pin to vss pin with the shortest possible wiring. reason: the processor mode of the microcomputer is influenced by a potential at cnvss pin when cnvss and vss pins are connected. if the noise causes a potential difference between cnvss and vss pins, the processor mode may become unstable. this may cause a microcomputer malfunction or a program runaway. fig. 6. wiring for clock input/output pins fig. 7. wiring for cnvss pin noise x in x out vss x in x out vss m37751 m37751 n o t a c c e p t a b l e a c c e p t a b l e noise cnvss vss m37751 cnvss vss m37751 a c c e p t a b l e n o t a c c e p t a b l e l l l
7751 group users manual 20C63 appendix appendix 8. examples of noise immunity improvement (4) wiring for cnvss (v pp ) pin of built-in prom version < in single-chip or memory expansion modes> l connect cnvss (v pp ) to vss pin of the microcomputer with the shortest possible wiring. l if the above countermeasure can not be taken, insert an approximate 5 k w resistor between cnvss (v pp ) and vss pins and be sure to make the distance between the resistor and cnvss (v pp ) pin as short as possible. < in microprocessor mode> l connect cnvss (v pp ) pin to vcc pin with the shortest possible wiring. reason: cnvss (v pp ) pin is connected to the internal rom in the low-impedance state. (noise is easily fed to the pin in this condition.) if noise enters the cnvss (v pp ) pin, incorrect instruction codes or data is fetched from the built-in prom. this may cause a program runaway. fig. 8. wiring for cnvss (v pp ) pin of built-in prom version microprocessor mode shortest possible distance cnv ss (v pp ) v cc m37751 shortest possible distance approx. 5 kohms cnvss pin is connected to vss pin with the shortest possible wiring. cnv ss (v pp ) v ss single-chip and memory expansion modes m37751 ] the above countermeasur e is not necessar y for byte (v pp ) pin. cnvss pin is connected to vss pin with the shortest possible wiring.
7751 group users manual 20C64 appendix appendix 8. examples of noise immunity improvement 2. connection of bypass capacitor between vss and vcc lines connect an approximate 0.1 f bypass capacitor as follows: l connect a bypass capacitor between the vss and vcc pins, at equal lengths. l the wiring connecting the bypass capacitor between the vss and vcc pins should be as short as possible. l use thicker wiring for the vss and vcc lines than the other signal lines. fig. 9. bypass capacitor between vss and vcc lines bypass capacitor aa aa aa aa aa aa aa aa aa aa aa aa vcc vss m37751 wiring pattern wiring pattern
7751 group users manual 20C65 appendix appendix 8. examples of noise immunity improvement 3. wiring for analog input pins, analog power source pins, etc. (1) processing analog input pins l connect a resistor to the analog signal line, which is connected to an analog input pin, and make the connection as close to the microcomputer as possible. l connect a capacitor between the analog input pin and avss pin, as close to the avss pin as possible. reason: a signal which is input to the analog input pin is usually an output signal from a sensor. the sensor which measures changes in status tends to be installed far from the microcomputer printed circuit board. the result is long wiring that becomes an antenna which picks up noise and feeds it into the microcomputer analog input pin. if a capacitor between an analog input pin and avss pin is grounded far away from avss pin, noise on the gnd line may enter the microcomputer through the capacitor. fig. 10. example of noise immunity improvement using thermistor an i avss thermistor noise m37751 ri ci reference value ri : approximately 100 to 1000 ci approximately 100 to 1000 pf notes 1 : design an external circuit for ani pin so that charge/discharge is available within 1 cycle of ad . 2 : this resistor and thermistor are used to divide resistance. (note 2) :
7751 group users manual 20C66 appendix appendix 8. examples of noise immunity improvement (2) processing analog power source pins, etc. l use independent power sources for vcc, avcc and v ref pins. l insert capacitors between the avcc and avss pins, and between the v ref and avss pins. reasons: prevents the a-d converter from noise on the vcc line. fig. 11. processing analog power source pins, etc. avcc avss m37751 reference value c1 0.47 f c2 0.47 f note : connect capacitors using the thickest, shortest wiring possible. v ref an i c1 c2 (sensor, etc.)
7751 group users manual 20C67 appendix appendix 8. examples of noise immunity improvement (2) distance oscillator from signal lines with frequent potential level changes l install an oscillator and a connecting pattern of an oscillator away from signal lines in which potential levels change frequently. l do not cross the signal lines over the clock-related or noise-sensitive signal lines. reason: signals lines with frequently changing potential levels may affect other signal lines at a rising or falling edge. in particular, if the lines cross over a clock-related signal line, clock waveforms may be deformed, which causes a microcomputer malfunction or a program runaway. 4. oscillator protection the oscillator which generates the basic clock for the microcomputer operations must be protected from the affect of other signals. (1) distance oscillator from signal lines with large current flows install the microcomputer, especially the oscillator, as far as possible from signal lines which handle currents larger than the microcomputer current value tolerance. reason: a microcomputer is used in systems which contain signal lines for controlling motors, leds, thermal heads, etc. noise occurs due to mutual inductance when a large current flows through the signal lines. fig. 12. connection of signal wires where a large current flows fig. 13. wiring of rapidly level changing signal wire x in x out vss m m37751 mutual inductance large current x in x out vss ] do not cross. m37751 ] i/o pin for signal with frequently changing potential levels.
7751 group users manual 20C68 appendix appendix 8. examples of noise immunity improvement (3) oscillator protection using vss pattern print a vss pattern on the bottom (soldering side) of a double-sided printed circuit board, under the oscillator mount position. connect the vss pattern to vss pin of the microcomputer with the shortest possible wiring, separating it from other vss patterns. fig. 14. vss pattern underneath mounted oscillator aa aa aa aa aa a a a a aa a a a a a a a a x in x out vss an example on the bottom of an oscillator. mounted pattern example of an oscillator unit. separate vss lines for oscillation and supply. m37751
7751 group users manual 20C69 appendix appendix 8. examples of noise immunity improvement 5. setup for i/o ports setup i/o ports by hardware and software as follows: l connect a resistor of 100 ohms or more to an i/o port in series. l as for an input port, read data several times for checking whether input levels are equal or not. l as for an output port, since the output data may reverse because of noise, rewrite data to its port pi register periodically. l rewrite data to port pi direction registers periodically. fig. 15. setup for i/o ports noise direction register port latch data bus port
7751 group users manual 20C70 appendix appendix 8. examples of noise immunity improvement 6. reinforcement of the power source line l for the vss and vcc lines, use thicker wiring than that of other signal lines. l when using a multilayer printed circuit board, the vss and vcc patterns must each be one of the middle layers. l the following is necessary for double-sided printed circuit boards: on one side, the microcomputer is installed at the center, and the vss line is looped or meshed around it. the vacant area is filled with the vss line. on the opposite side, the vcc line is wired the same as the vss line. the power source lines of external devices which are connected by bus to the microcomputer must be connected to the microcomputer's power source lines with the shortest possible wiring. reasons: with external devices connected to the microcomputer, the levels of many of the signal lines (total external address buses: 24 bits) may change simultaneously, causing noise on the power source line.
appendix 7751 group users manual 20C71 appendix 9. q & a appendix 9. q & a information which may be helpful in fully utilizing the 7751 group is provided in q & a format. in q & a, as a rule, one question and its answer are summarized within one page. the upper box on each page is a question, and a box below the question is its answer. (if a question or an answer extends to two or more pages, there is a page number at the lower right corner.) at the upper right corner of each page, the main function related to the contents of description in that page is listed.
appendix appendix 9. q & a 7751 group users manual 20C72 interrupt q if an interrupt request (b) occurs while executing an interrupt routine (a), is the main routine is not executed before the intack sequence for the next interrupt (b) is executed after the interrupt routine (a) under execution is completed? (2) if the next interrupt request (b) occurs immediately after generating of the sampling pulse , the microcomputer executes one instruction of the main routine before executing the intack se- quence for (b) because the interrupt request is sampled by the next sampling pulse . sampling for interrupt requests are performed by sampling pulses generated synchronously with the cpus op-code fetch cycles. (1) if the next interrupt request (b) occurs before the sampling pulse ( ) for the rti instruction is generated, the microcomputer executes the intack sequence for (b) without executing the main routine (not even one instruction) because sampling is completed while executing the rti instruction. a condition l i is cleared to 0 with the rti instruction. l the interrupt priority level of the interrupt (b) is higher than the main routine ipl. l the interrupt priority detection time is 2 cycles of f. interrupt routine (a) main routine intack sequence for interrupt (b) sequence of execution rti instruction ? intack sequence for interrupt (b) interrupt request (b) interrupt routine (a) sampling pulse rti instruction main routine interrupt request (b) sampling pulse intack sequence for interrupt (b) one instruction executed interrupt routine (a) rti instruction
appendix 7751 group users manual 20C73 appendix 9. q & a interrupt there is a routine where a certain interrupt request should not be accepted (with enabled acceptance of all other interrupt requests). accordingly, the program set the interrupt priority level select bits of the interrupt to be not accepted to 000 2 in order to disable it before executing the routine. however, the interrupt request of that interrupt has been accepted immediately after the priority level had been changed. why did this occur and what can i do about it? when changing the interrupt priority level, the microcomputer can behave as if the interrupt request is accepted immediately after it is disabled if the next instruction (the lda instruction in the above case) is already stored in the bius instruction queue buffer and conditions to accept the interrupt request which should not be accepted are met immediately before executing the instruction which is in that buffer. when writing to a memory or an i/o, the cpu passes the address and data to the biu. then, the cpu executes the next instruction in the instruction queue buffer while the biu is writing data into the actual address. detection of interrupt priority level is performed at the beginning of each instruc- tion. in the above case, in the interrupt priority detection which is performed simultaneously with the execution of the next instruction, the interrupt priority level before changing it is detected and the interrupt request is accepted. it is because the cpu executes the next instruction before the biu finishes changing the interrupt priority levels. q a (1/2) interrupt request is accepted in this interval : ldm #00h, xxxic ; writes 000 2 to interrupt priority level select bits. ; clears interrupt request bit to 0. lda a,data ; instruction at the beginning of the routine that should not accept one certain interrupt request. :; previous instruction executed (instruction prefetch) cpu operation biu operation interrupt priority detection time sequence of execution interrupt priority level select bits set change of interrupt priority levels completed interrupt request accepted interrupt request generated ldm instruction executed lda instruction executed
appendix appendix 9. q & a 7751 group users manual 20C74 interrupt (2/2) a to prevent this problem, use software to execute the routine that should not accept a certain interrupt request after change of interrupt priority level is completed. the following shows a sample program. [ sample program ] after an instruction which writes 000 2 to the interrupt priority level select bits, fill the instruc- tion queue buffer with the nop instruction to make the next instruction not be executed before the writing is completed. : ldm #00h, xxxic ; sets the interrupt priority level select bits to 000 2 . nop ; nop ; nop ; lda a,data ; instruction at the beginning of the routine that should not accept a certain interrupt request
appendix 7751 group users manual 20C75 appendix 9. q & a interrupt q (1) in both the edge sense and level sense, external interrupt requests occur when the input ____ signal to the int i pin changes its level regardless of clock f 1 . in the edge sense, the interrupt request bit is set to 1 at this time. (2) there are two methods: one uses external interrupts level sense, and the other uses the timers event counter mode. using external interrupts level sense ____ in hardware, input a logical sum of multiple interrupt signals (e.g., a, b, and c) to the int i pin, and input each signal to each corresponding port. ___ in software, check the ports input levels in the int i interrupt routine to determine that which of the signals a, b, and c is input. a (1) ____ which timing of clock f 1 is the external interrupts (input signals to the int i pin) detected? (2) ____ how can four or more external interrupt input pins (int i ) be used? using timers event counter mode in hardware, input interrupt signals to the tai in pins or tbi in pins. in software, set the timers operating mode to the event counter mode and a value 0000 16 into the timer register to the effective edge. the timers interrupt request occurs when an interrupt signal (selected effective edge) is input. m37751 port port port int i
appendix appendix 9. q & a 7751 group users manual 20C76 ____ in the case selecting the cts function in uart (clock asynchronous serial i/o) mode, when the ____ transmitting side check the cts input level ? it is check near the middle of the stop bit (when two stop bits are selected, the second stop bit). a q serial i/o (uart mode) d 6 n: 1-bit length d 7 sp sp . . . . . . . . . . . . . . . . . . . . . . . . . . . . nnn n/2 n/2 d 6 transmit data d 7 sp . . . . . . . . . . . . . . . . . . . . . . . . . . . . nn n/2 n/2 input level to cts i pin is checked near here. transmit data nput level to cts i pin is checked near here. i
appendix 7751 group users manual 20C77 appendix 9. q & a ______ when l level is input to the hold pin, how long is the bus actually opened ? a the bus is opened after 50 ns at maximum has passed from the rising edge of next clock f 1 when ____ the hlda pin output becomes l level. q hold function ....... term where bus is open clock 1 hold hlda t pxz(hold-pz) : maximum 50 ns
appendix appendix 9. q & a 7751 group users manual 20C78 processor mode if the processor mode is switched as described below by using the processor mode bits (bits 1 and 0 at address 5e 16 ) during program execution, is there any precaution in software? l single-chip mode ? microprocessor mode l memory expansion mode ? microprocessor mode q a if the processor mode is switched as described above by using the processor mode bits, the mode is switched simultaneously when the cycle to write to the processor mode bits is completed. then, the program counter indicates the address next to the address (address xxxx 16 ) that contains the write instruction for the processor mode bits. additionally, access to the internal rom area is disabled. however, since the instruction queue buffer can prefetch up to three instructions, the address in the external rom area and is accessed first after the mode is switched is one of xxxx 16 + 1 to xxxx 16 + 4. the instructions at addresses xxxx 16 + 1 to xxxx 16 + 3 in the internal rom area can be executed. to prevent this problem, process the following by software. write the write instruction for the processor mode bits and next instructions (at least three bytes) at the same addresses both in the internal rom and external rom areas. (see below.) transfer the write instruction for the processor mode bits to an internal ram area and make a branch to there in order to execute the write instruction. after that, make a branch to the program address in the external rom area. (contents of the instruction queue buffer is initialized by a branch instruction.) ldm . b #00000010b, pmr nop nop nop ldm . b #00000010b, pmr nop nop nop xxxx 16 external rom area internal rom area xxxx 16 at least three bytes : : : : : : :
appendix 7751 group users manual 20C79 appendix 9. q & a sfr q is there any sfr for which instructions that can be used to set registers or bits are limited? use the sta or ldm instruction to set the registers or the bits listed below. do not use read- modify-write instructions (i.e., clb, seb, inc, dec, asl, asr, lsr, rol, and ror ). uart0 baud rate register (address 31 16 ) uart1 baud rate register (address 39 16 ) uart0 transmit buffer register (addresses 33 16 , 32 16 ) uart1 transmit buffer register (addresses 3b 16 , 3a 16 ) timer a4 two-phase pulse signal processing select bit (bit 7 at address 44 16 ) timer a3 two-phase pulse signal processing select bit (bit 6 at address 44 16 ) timer a2 two-phase pulse signal processing select bit (bit 5 at address 44 16 ) a
appendix appendix 9. q & a 7751 group users manual 20C80 clock q is there any precaution when f(x in ) > 25 mhz ? a 0 0 0 0 0 0 fix these bits to 0. bus cycle when accessing external device b5 b4 0 0 : 5 f 0 1 : 4 f 1 0 : 3 f (1 1: not selected) fix these bits to 0. set the processor mode register 1 (address 5f 16 ) to the following. the microcomputer becomes the following state by the setting above. l f 4 , f 32 , f 128 , or f 1024 can be selected for the operating clock of internal peripheral devices such as timer. l sfr and internal rom area are accessed at 3 f bus cycle. internal ram area is accessed at 2 f bus cycle. l 3 f , 4 f , or 5 f can be selected for the bus cycle when accessing an external device. 2 f cannot be selected for the bus cycle. b7 b0
appendix 7751 group users manual 20C81 appendix 9. q & a q is there any precaution when f(x in ) 25 mhz ? when setting the cpu running speed select bit (bit 3 at address 5f 16 ) to 1, sfr and internal rom access become faster than this bit is 0. accordingly, we recommend to set this bit to 1. however, do not set bits 5 to 3 at address 5f 16 to 001 2 . when setting bit 3 at address 5f 16 to 1, set bit 5, bit 4, or both bits 5 and 4 to 1 at the same time because bits 5 and 4 at address 5f 16 become 00 2 at reset. clock a 0 0 1 bus cycle when accessing external device set these bits to 01 2 , 10 2 , 11 2 . (not selected 00 2 .) fix these bits to 0. clock source for peripheral devices 0 : f divided by 2 1 : f fix these bits to 0. b5 b4 0 0 : 4 f 0 1 : 3 f 1 0 : 2 f b7 b0 0 0
appendix appendix 9. q & a 7751 group users manual 20C82 are there precautions when the 7751 series substitutes for the 7700 series or the 7750 series? substitute for 7700 series/7750 series the common precautions are described below. refer to the relevant chapter for details. ?fix the processor status register (ps) bits 15 to 11 to 0. do not set these bits to 1. ?there are the structure differences in the processor mode register 0 (address 5e 16 ) and the processor mode register 1 (address 5f 16 ). ?the a-d conversion interrupt request bit (bit 3 at address 70 16 ) is undefined at reset. set this bit to 0 by software before use. ?clear the receive enable bit (bit 2 at addresses 35 16 , 3d 16 ) to 0 when clearing the overrun error flag (bit 4 at addresses 35 16 , 3d 16 ) to 0. this is only method that the overrun error flag is cleared to 0 ?there are instructions of which number of the instruction cycle is decreased. accordingly, it is possible that the instruction execution timing become faster. ?part of the electrical characteristics, ready function, hold function, and the bus timing are different. a q
appendix 7751 group users manual 20C83 appendix 9. q & a watchdog timer when detecting the software runaway by the watchdog timer, if not software reset but setting the same value as the contents of the reset bector address to the watchdog timer interrupt bector address is processed, how does it result in? when branching to the reset branch address within the watchdog timer interrupt routine, how does it result in? a the cpu registers and the sfr are not initialized in the above-mentioned way. accordingly, the user must perform the initial setting for these all by software. the processor interrupt priority level (ipl) retains 7 of the watchdog timer interrupt priority level, and that is not initialized. consequently, all interrupt requests are not accepted. when rewriting the ipl by software, save once the 16-bit immediate value to the stack area and next restore that 16-bit immediate value to all bits of the processor status register (ps). we recommend software reset in order to initialize the microcomputer for software runaway. q
appendix appendix 9. q & a 7751 group users manual 20C84 memorandum
glossary
glossary 7751 group users manual 2 this section briefly explains the terms used in this users manual. the terms defined here apply to this manual only. meaning means performing read, write, or read and write. an accessible memory space of up to 16 mbytes. means whether accessible or not. means a transfer rate of serial i/o. means moving the programs execution point (= address) to another location. _ ____ __ ____ _____ _____ a generic name for ale, e, bhe, r/w, rdy, hold, hlda and byte signals. a signal that is counted by timers a and b, the uarti baud rate register (brgi) and watchdog timer. that is f 2 /f 4 , f 16 /f 32 , f 64 /f 128 , f 512 /f 1024 selected by the count source select bits and others. means decreasing by 1 and counting. an accessible area for external devices connected in the memory expansion or microprocessor mode. it is up to 16-mbyte external area. a generic name for the external address bus and the data bus. devices connected externally to the microcomputer. a generic name for a memory, an i/o device and a peripheral ic. an accessible internal area. a generic name for areas of the internal ram, internal rom and the sfr. a routine that is automatically executed when an interrupt request is accepted. set the start address of this routine into the interrupt vector address. means a transfer data format of serial i/o; lsb is transferred first. means a transfer data format of serial i/o; msb is transferred first. a state where the up-count resultant is greater than the counter resolution. an instruction that reads the memory contents, modifies them and writes back to the same address. relevant instructions are the asl , asr , clb , dec , inc , lsr , rol , ror , seb instructions. a generic name for bus control, address bus, and data bus signals. a state where the oscillation circuit halts and the program execution is stopped. by executing the stp instruction, the microcomputer enters stop mode. clock asynchronous serial i/o. when used to designate the name of a functional block, this term also means the serial i/o which can be switched to the cock synchronous serial i/o. a state where the down-count resultant is greater than the counter resolution. relevant term access access up-count internal area external area msb first lsb first under flow up-count bus control signal wait mode clock synchronous serial i/o. overflow down-count term access access space access characteristics baud rate branch bus control signal count source down-count external area external bus external device internal area interrupt routine lsb first msb first overflow read-modify-write instruction signal required for access to external device stop mode uart under flow
glossary 7751 group users manual 3 meaning means increasing by 1 and counting. a state where the oscillation circuit is operating, however, the program execution is stopped. by executing the wit instruction, the microcomputer enters wait mode. relevant term down-count stop mode term up-count wait mode
glossary 7751 group users manual 4 memorandum
mitsubishi semiconductors users manual 7751 group jul. first edition 1997 editioned by committee of editing of mitsubishi semiconductor users manual published by mitsubishi electric corp., semiconductor marketing division this book, or parts thereof, may not be reproduced in any form without permission of mitsubishi electric corporation. ?1997 mitsubishi electric corporation

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